TW201637102A - 半導體封裝及其製造方法 - Google Patents
半導體封裝及其製造方法 Download PDFInfo
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- TW201637102A TW201637102A TW105109982A TW105109982A TW201637102A TW 201637102 A TW201637102 A TW 201637102A TW 105109982 A TW105109982 A TW 105109982A TW 105109982 A TW105109982 A TW 105109982A TW 201637102 A TW201637102 A TW 201637102A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 246
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 50
- 239000011347 resin Substances 0.000 claims abstract description 113
- 229920005989 resin Polymers 0.000 claims abstract description 113
- 239000000463 material Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims abstract description 15
- 235000012431 wafers Nutrition 0.000 claims description 117
- 238000007747 plating Methods 0.000 claims description 51
- 238000000034 method Methods 0.000 claims description 28
- 239000010949 copper Substances 0.000 claims description 23
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- 229910052802 copper Inorganic materials 0.000 claims description 21
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 239000010931 gold Substances 0.000 claims description 6
- 229910052759 nickel Inorganic materials 0.000 claims description 5
- 230000004888 barrier function Effects 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 4
- 229910052737 gold Inorganic materials 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 2
- 238000000576 coating method Methods 0.000 claims 2
- 239000013078 crystal Substances 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- 230000004048 modification Effects 0.000 description 52
- 238000012986 modification Methods 0.000 description 52
- 238000005530 etching Methods 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 239000010936 titanium Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- JNDMLEXHDPKVFC-UHFFFAOYSA-N aluminum;oxygen(2-);yttrium(3+) Chemical compound [O-2].[O-2].[O-2].[Al+3].[Y+3] JNDMLEXHDPKVFC-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007613 environmental effect Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910019901 yttrium aluminum garnet Inorganic materials 0.000 description 2
- 208000013201 Stress fracture Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 108091008695 photoreceptors Proteins 0.000 description 1
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- H—ELECTRICITY
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- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H01L23/528—Geometry or layout of the interconnection structure
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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Abstract
降低自半導體晶片之元件表面至半導體封裝之表面之熱阻抗為目的之一。此外,易於實現金屬之分割圖案化,大幅降低因矽與金屬之熱膨脹係數差異而發生之應力,且提升對應環境之可靠度為目的之一。再者,藉由不使用TIM材料製造半導體封裝而實現成本降低亦為目的之一。在此提供一種半導體封裝包含半導體晶片、第一配線及第二配線。半導體晶片具有配置有電極之元件表面及相反於此元件表面之背表面,樹脂覆蓋半導體晶片。第一配線直接連接至此電極或經由配置於此樹脂之第一開口部連接至此電極。第二配線經由配置於此樹脂之第二開口連接至此背表面。
Description
本發明之一實施型態為關於企圖降低半導體封裝之熱阻抗且提升半導體封裝之環境可靠度之技術。
以往之半導體封裝結構中,一般會將熱介面材料(Thermal Interface Material,TIM)使用於半導體晶片及搭載半導體晶片之晶粒墊(die pad)之間之熱連接及機械連接。TIM大致上分為將銀膠等之熱傳導性高之物質浸漬於樹脂之材料,以及焊料等金屬熔融接合之材料。
樹脂浸漬類型之TIM具有因彈性係數而能緩和應力之優點。然而,其本身之材料強度不算強,而具有於溫度循環試驗等之對應環境試驗中容易受到破壞之問題。再者,其熱傳導率亦不算高,而具有難以滿足功率裝置(power device)等所要求之規格之問題。此外,金屬熔融接合類型之TIM之熱傳導率較佳。然而,由於半導體晶片及晶粒墊之熱膨脹係數差異所造成之應力非常大,即使斷裂強度較高,仍具有容易伴隨熱膨脹係數差異而發生應力破壞之問題。
本發明之一實施型態之一目的,為藉由於半導體晶片之配置有電極之元件表面直接進行金屬化(matelize),而降低自半導體晶片之配置有電極之元件表面至半導體封裝之表面之熱阻抗。
本發明之一實施型態之一目的,為藉由於半導體晶片之未配置有電極之背表面直接進行金屬化,而降低自半導體晶片之背表面至半導體封裝之表面之熱阻抗。
本發明之一實施型態之一目的,亦為藉由於製造過程中應用鍍覆(plating)處理,而易於實現金屬之分割圖案化,大幅降低因矽與金屬之熱膨脹係數差異而發生之應力,且提升對應環境之可靠度。
本發明之一實施型態之一目的,亦為藉由不使用TIM材料製造半導體封裝而實現成本降低。
關於本發明之一實施型態之半導體封裝,其包含半導體晶片、第一配線及第二配線。半導體晶片具有配置有電極之元件表面及相反於元件表面之背表面,樹脂覆蓋半導體晶片。第一配線直接連接至元件表面或經由配置於樹脂之第一開口部連接至元件表面。第二配線經由配置於樹脂之第二開口連接至背表面。
關於本發明之一實施型態之半導體封裝,其包含多個半導體晶片、第一配線、第二配線及第三配線。各個半導體晶片具有配置有電極之元件表面及相反於元件表面之背表面,樹脂覆蓋多個半導體晶片。第一配線直接連接至元件表面,或者經由配置於樹脂之第一開口部連接至元件表面。第二配線經由配置於樹脂之第二開口部連接至背表面。第三配線設置於配置有第二配線之樹脂之層體,且經由配置於樹脂之多個第三開口部電性連接至第一配線。第三配線電性連接多個半導體晶片中之相異之半導體晶片之電極。
關於本發明之一實施型態之半導體封裝之製造方法包含以下步驟。令半導體晶片載置於固定材之上,其中半導體晶片之配置有電極之元件表面朝上且相反於元件表面之背表面朝下。於固定材上填充第一樹脂以埋設半導體晶片。於第一樹脂形成露出元件表面之第一開口部。於元件表面上以鍍覆法形成第一配線。去除固定材。於背表面及第一樹脂上填充第二樹脂。於第二樹脂形成露出背表面之第二開口部。於第二樹脂上形成抗鍍件(plating resist)。於背表面上以鍍覆法形成第二配線。
關於本發明之一實施型態之半導體封裝之製造方法包含以下步驟。令多個半導體晶片載置於固定材之上,其中各個半導體晶片之配置有電極之元件表面朝上且相反於元件表面之背表面朝下。於固定材上填充第一樹脂以埋設半導體晶片。於第一樹脂形成露出元件表面之第一開口部。於元件表面上以鍍覆法形成第一配線。去除固定材。於背表面及第一樹脂上填充第二樹脂。於第二樹脂形成露出背表面之第二開口部及露出第一配線之第三開口部。於第二樹脂上形成抗鍍件。於第二開口部、第三開口部及第二樹脂上鍍銅,以於第二開口部及第二樹脂上形成第二配線,且於第三開口部及第二樹脂上形成第三配線。第三配線電性連接多個半導體晶片中之相異之半導體晶片之電極。
關於本發明之一實施型態之半導體封裝之製造方法包含以下步驟。於支撐板塗布感光性阻件。於感光性阻件之一部分開設開口。於開口以鍍覆法形成第一配線。準備半導體晶片,其具有配置有電極之元件表面及相反於元件表面之背表面,以連接第一配線及電極之方式覆晶(flip chip)連接半導體晶片至第一配線上。於支撐板上填充樹脂以埋設半導體晶片及第一配線。於樹脂形成露出背表面之開口部。於樹脂上形成抗鍍件。於背表面上以鍍覆法形成第二配線。
關於本發明之一實施型態之半導體封裝之製造方法包含以下步驟。於支撐板塗布感光性阻件。於感光性阻件之一部分開設開口。於開口以鍍覆法形成第一配線。準備多個半導體晶片,各個半導體晶片具有配置有電極之元件表面及相反於元件表面之背表面,以連接第一配線及電極之方式覆晶連接多個半導體晶片至第一配線上。於支撐板上填充樹脂以埋設多個半導體晶片及第一配線。於樹脂形成露出背表面之開口部及露出第一配線之開口部。於樹脂上形成抗鍍件。於露出背表面之開口部、露出第一配線之開口部及樹脂上鍍銅,以於露出背表面之開口部及樹脂上形成第二配線,且於露出第一配線之開口部及樹脂上形成一第三配線。第三配線電性連接多個半導體晶片中之相異之半導體晶片之電極。
根據本發明之一實施型態,能夠降低自半導體晶片之配置有電極之元件表面至半導體封裝之表面之熱阻抗。此外,能夠易於實現金屬之分割圖案化,能夠大幅降低因矽與金屬之熱膨脹係數差異而發生之應力,且能夠提升對應環境之可靠度。再者,藉由不使用TIM材料製造半導體封裝而實現成本降低。
以下,將參照圖式說明關於本發明之實施型態。然而,關於本發明之半導體裝置能夠以多種相異之態樣實施,而並非限定解釋為以下所示之實施型態之記載內容。另外,以本實施型態參照之圖式中,相同部分或具有相同功能之部分將附上相同符號,且省略重覆的說明。
以下將說明第一實施型態。
使用圖1至圖12說明關於第一實施型態之半導體封裝100之結構及其製造方法。
以下將說明半導體封裝之整體結構。
圖1為繪示關於本發明之第一實施型態之半導體封裝100之整體構造之概略圖。半導體晶片20埋設於樹脂40之中。第二配線70經由導電通孔(via,圖未繪示)連接至半導體晶片20之上表面。而且,第一配線(圖未繪示)形成於半導體封裝100之下側,且直接連接至半導體晶片20之電極(圖未繪示)。再者,第一配線及配線80經由導電通孔電性連接。
以下將說明關於第一實施型態之半導體封裝之製造方法。
圖2至圖12為依序繪示關於本發明之第一實施型態之半導體封裝100之製造流程之圖,且為繪示位於圖1之I-I’線之剖面圖。
圖2繪示於支撐板11上形成感光性的光阻件(photo resist)13之狀態。支撐板11能夠適當利用蝕刻性優良之銅(Cu)等材料。
圖3繪示自圖2經過光刻(photolithography)流程後之狀態。於光阻件13以指定之配線圖案曝光顯影,進而形成開口部。
然而,雖然於圖2及圖3中已說明應用感光性的光阻件13之形成方法,但亦能夠應用非感光性的阻件取代光阻件13。取代光阻件13而應用非感光性的阻件之場合中,與圖2同樣地將非感光性的阻件配置於支撐板11之後,藉由準分子雷射(excimer laser)、二氧化碳雷射、釔鋁石榴石(yttrium aluminum garnet,YAG)雷射等方式形成開口部。
圖4繪示藉由鍍覆方式形成第一配線60之狀態。第一配線60可適當使用銅等金屬。為了保護外部端子,第一配線60可於最下層實施鍍金(Au),接下來實施鍍鎳(Ni)做為銅蝕刻之障壁金屬(barrier metal),再實施鍍銅。其中,障壁金屬亦可藉由多層之金屬層構成,例如亦可為鈦(Ti)/銅、鈦/鎳/金、鈦/鎳/銀(Ag)。
形成第一配線60之後,剝離或去除光阻件13(參照圖5)。
接下來,藉由覆晶工法將半導體晶片20載置於第一配線60上(參照圖6)。半導體晶片20具有配置有電極26之元件表面22及相反於元件表面22之背表面24。其中,本說明書中之「元件表面」包含設置有電極之部分及未設置有電極之半導體晶片之表面。以將電極26連接至第一配線60之方式,將半導體晶片20裝設成元件表面22位於下側(靠近第一配線之位置)。
接下來,以密封形成於支撐板11上之第一配線60及半導體晶片20之方式,藉由真空壓製法(vacuum press method)填充樹脂40(參照圖7)。樹脂40亦可使用非感光性樹脂或感光性樹脂等材料。
接下來,於填充完成之樹脂40開設開口部41及開口部42(參照圖8)。以開口部41露出半導體晶片20之背表面24且開口部42露出第一配線60之方式,於各自之指定位置形成開口部41及開口部42。露出半導體晶片20之背表面24之開口部41,亦可為隨著半導體晶片20之形狀而具有較大口徑之矩形開口。
於樹脂40使用非感光性樹脂之場合中,可應用準分子雷射等方式開設開口部41及開口部42。於樹脂40使用感光性樹脂之場合中,可藉由應用曝光顯影法開設開口部41及開口部42。於樹脂40開設開口部41及開口部42之後,可藉由全面濺射(sputter)法形成鈦、銅等之蒸鍍膜。
接下來,於樹脂40上之指定位置形成抗鍍件14(參照圖9)。抗鍍件14亦可藉由曝光顯影法形成。
接下來,於開口部41及開口部42濺射形成種子膜之後,藉由鍍覆法(plating method)於開口部41及開口部42填充鍍覆銅材料。再者,藉由鍍覆法於經過鍍銅之開口部41及其周邊之樹脂40上填充鍍覆銅材料,以形成第二配線70。同樣地,於經過鍍銅之開口部42及其周邊之樹脂40上形成配線80(參照圖10)。抗鍍件14配置成使第二配線70與配線80不接觸。
接下來,剝離或去除抗鍍件14(參照圖11)。而且,可藉由蝕刻法去除種子膜。
最後,可藉由蝕刻法去除支撐板11,而完成半導體封裝100(參照圖12)。
關於本發明之第一實施型態之半導體封裝100中,經由大口徑之開口部41,而於半導體晶片20之背表面24藉由直接進行金屬化以形成第二配線70。藉由具有如此之結構,能夠降低自半導體晶片20之背表面24至形成於半導體封裝100之表面之第二配線70之熱阻抗。此外,由於不需要使用先前技術之TIM材料,而亦能夠實現成本降低。
以下將說明第二實施型態。
接下來,將說明關於第二實施型態之半導體封裝200之結構及其製造方法。其中,半導體封裝200之整體構造可與以第一實施型態說明之圖1相同。
以下將說明關於第二實施型態之半導體封裝之製造方法。
圖13至圖25為依序繪示關於本發明之第二實施型態之半導體封裝200之製造流程之圖,且為繪示位於圖1之I-I’線之剖面圖。
圖13繪示於支撐板11上形成臨時固定材16之狀態。支撐板11能夠適當利用蝕刻性優良之銅等材料。而且,於第二實施型態之製造流程中為了臨時固定半導體晶片20而形成之臨時固定材16,可例如使用樹脂等材料。
接下來,於臨時固定材16上配置成半導體晶片20之背表面24接觸於臨時固定材16(參照圖14)。亦即,以半導體晶片20之設置有電極26之元件表面22朝上之方式,將半導體晶片20配置於臨時固定材16上。
接下來,以密封半導體晶片20之元件表面22及側表面之方式,於臨時固定材16及半導體晶片20上填充樹脂40(參照圖15)。
接下來,於樹脂40開設開口部43、開口部44及開口部45(參照圖16)。於此,以露出半導體晶片20之電極26之方式形成開口部43及開口部44。然而,此些開口部43、44並非必須以僅露出電極26之方式形成,亦可以露出半導體晶片20之未配置有電極26之半導體晶片20之表面之方式形成。此外,形成開口部45之深度為自樹脂40之上表面至半導體晶片20之配置有電極26之位置之範圍,且開口部45之一部分可與開口部44重疊。亦即於開口部45及開口部44之製造流程中,可先形成開口部45,再於開口部45之一部分且於露出電極26之指定位置形成開口部45。
接下來,藉由鍍覆法於開口部43、開口部44及開口部45填充鍍覆銅材料。於開口部43、開口部44及開口部45分別形成導電通孔63、導電通孔64及第一配線60(參照圖17)。
接下來,去除支撐板11及臨時固定材16(參照圖18)。
接下來,於支撐板12之上表面形成固定材17,並上下翻轉於圖18所示之半導體晶片20、樹脂40、第一配線60等構成之結構體,且將此結構體載置於支撐板12(參照圖19)。亦即固定材17接觸於形成有第一配線60之表面,且以半導體晶片20之背表面24朝上之方式載置半導體晶片20。
接下來,於半導體晶片20之背表面24及樹脂40之上側進一步填充樹脂(參照圖20)。以下,將先前已形成之樹脂40與此流程中所填充之樹脂合併稱為樹脂40,再進行說明。
接下來,於填充完成之樹脂40開設開口部46及開口部47(參照圖21)。以開口部46露出半導體晶片20之背表面24且開口部47露出第一配線60之方式,於各自之指定位置形成開口部46及開口部47。露出半導體晶片20之背表面24之開口部46,亦可為隨著半導體晶片20之形狀而具有較大口徑之矩形開口。
接下來,於樹脂40上之指定位置形成抗鍍件15(參照圖22)。
接下來,藉由鍍覆法於開口部46及開口部47填充鍍覆銅材料,以形成導電通孔71及導電通孔81。再者,藉由鍍覆法於導電通孔71及其周邊之樹脂40上填充鍍覆銅材料,以形成第二配線70。同樣地,於導電通孔81及其周邊之樹脂40上形成配線80(參照圖23)。抗鍍件15配置成使第二配線70與配線80不接觸。
接下來,剝離或去除抗鍍件15(參照圖24)。而且,可藉由蝕刻法去除種子膜。
最後,可去除支撐板12及固定材17,而完成半導體封裝200(參照圖25)。
關於本發明之第二實施型態之半導體封裝200中,亦經由大口徑之開口部41,而於半導體晶片20之背表面24藉由直接進行金屬化以形成第二配線70。藉由具有如此之結構,能夠降低自半導體晶片20之背表面24至形成於半導體封裝200之表面之第二配線70之熱阻抗。此外,由於不需要使用先前技術之TIM材料,而亦能夠實現成本降低。
根據本發明之第二實施型態,由於高溫環境中焊料與電極或導電通孔之間不會發生金屬間化合物之成長,故相較於一般以焊料做為接合材料進行覆晶連接之場合,藉由以鍍覆法形成半導體晶片20之電極26與第一配線60之間之導電通孔63、64,而能夠實現高可靠度之半導體封裝200。更甚者,於半導體晶片20之未配置有電極26之部分設置有開口部46、47,且填充鍍覆此開口部46、47,故能夠自半導體封裝200之雙面進行冷卻,進而能夠實現低熱阻抗之半導體封裝200。
以下將說明變形例。
於第一實施型態及第二實施型態中,樹脂40隨著半導體晶片20之形狀開設較大口徑之矩形的開口部41或開口部46,且藉由鍍覆法形成導電通孔71。於此,由於光刻圖案化能夠易於實現金屬之分割圖案化,故能夠易於形成以下所示之分割圖案化。
圖26A及圖26B為繪示關於本發明之第一實施型態或第二實施型態之半導體封裝之變形例1之圖。圖26B為繪示半導體封裝之垂直剖面圖。再者,圖26A為繪示位於圖26B之II-II’線之水平剖面圖。其中,虛線20’所圍成之區域表示半導體晶片20(圖未繪示)之配置場所。
相較於第一實施型態及第二實施型態,變形例1相異於圖9所示之第一實施型態形成開口部41之流程,亦相異於圖21所示之第二實施型態形成開口部46之流程。於變形例1中,形成於俯視時垂直與水平為4×4個較小的矩形開口部。藉由鍍覆法於此接開口部填充銅材料以形成導電通孔72。形成導電通孔72之後與第一實施型態及第二實施型態同樣地,於導電通孔72及其周邊之樹脂40上形成第二配線70。
圖27A及圖27B為繪示關於本發明之第一實施型態或第二實施型態之半導體封裝之變形例2之圖。圖27B為繪示半導體封裝之垂直剖面圖。再者,圖27A為繪示位於圖27B之II-II’線之水平剖面圖。於變形例2中,分別形成有圓形的導電通孔73a、環狀的導電通孔73b、73c及具有環狀之一部分之形狀之導電通孔73d,此些導電通孔73a、73b、73c、73d於俯視時自半導體晶片20之中心位置以同心圓之方式擴展。形成導電通孔73a、73b、73c、73d之後之流程可與變形例1相同。
圖28A及圖28B為繪示關於本發明之第一實施型態或第二實施型態之半導體封裝之變形例3之圖。圖28B為繪示半導體封裝之垂直剖面圖。再者,圖28A為繪示位於圖28B之II-II’線之水平剖面圖。於變形例3中,雖與第一實施型態及第二實施型態同樣地隨著半導體晶片20之形狀形成矩形的導電通孔74,但於俯視時之導電通孔74之內側具有不形成導電通孔之導電通孔非形成部75a、75b、75c、75d。導電通孔非形成部75a、75b、75c、75d具有L字形,且以彼此為旋轉90度之方向形成。導電通孔非形成部75a、75b、75c、75d分別配置於如圖所示之四邊形之角落。
變形例1及變形例2中,能夠藉由光刻方式以俯視時所希望之形狀形成之導電通孔72、73a、73b、73c、73d以連接半導體晶片20之背表面24及第二配線70。換言之,於半導體晶片20及第二配線70之間,不僅能夠形成導電通孔72、73a、73b、73c、73d,還能夠於所希望之位置夾設而形成有樹脂40。藉由如此之構造,相較於第一實施型態及第二實施型態,變形例1及變形例2能夠提升分散半導體晶片20及第二配線70之熱膨脹係數差異所造成之應力之效果。
變形例3中,第二配線70不形成於導電通孔非形成部75a、75b、75c、75d上。亦即變形例3中,形成導電通孔74之後於導電通孔非形成部75a、75b、75c、75d上形成抗鍍件(圖未繪示)。再者,於形成第二配線70之後去除此抗鍍件。
圖29A及圖29B為繪示關於本發明之第一實施型態或第二實施型態之半導體封裝之變形例4之圖。圖29B為繪示半導體封裝之垂直剖面圖。再者,圖29A為繪示位於圖29B之II-II’線之水平剖面圖。於變形例4中,與第一實施型態同樣地隨著半導體晶片20之形狀形成矩形的導電通孔76,與變形例3同樣地於俯視時之導電通孔76之內側形成導電通孔非形成部77a、77b、77c、77d。導電通孔非形成部77a、77b、77c、77d具有圓弧形。導電通孔非形成部77a、77b、77c、77d分別配置成藉由導電通孔非形成部77a、77b、77c、77d而顯示出一個圓形。
與變形例1及變形例2相異,變形例3及變形例4中於垂直平面時,能夠不形成第二配線70於導電通孔非形成部75a、75b、75c、75d、77a、77b、77c、77d之上部。藉由具有如此之結構,而能夠更加提升分散半導體晶片20及第二配線70之熱膨脹係數差異所造成之應力之效果。
以下將說明第三實施型態。
使用圖30至圖33說明關於第三實施型態之半導體封裝300之結構及其製造方法。
圖30為關於本發明之第三實施型態之半導體封裝300之水平方向之剖面圖,圖31至圖33為垂直方向之剖面圖。圖30為位於圖31及圖32之C-C’線之水平剖面圖。圖31為位於圖30之A-A’線之垂直剖面圖。圖32為位於圖30之B-B’線之垂直剖面圖。而且,圖33為位於圖30之D-D’線之垂直剖面圖。
參照圖30至圖32時,可知半導體封裝300中並列配置半導體晶片320及半導體晶片420之二個半導體晶片。半導體封裝300之製造方法與關於第一實施型態之半導體封裝100之製造方法相同,或者與關於第二實施型態之半導體封裝200之製造方法相同。然而,半導體封裝300中雖配置二個半導體晶片320、420,但與第一實施型態及第二實施型態相異。其中,半導體封裝300之差異點在於形成與第二配線370、470同層之第三配線390。其中,能夠藉由應用光刻技術等技術而如以下所說明之結構形成半導體封裝300之各個配線。
半導體封裝300具有導電通孔381a、381b、481a、481b。而且,圖30中之符號381a、381b、481a、481b分別表示配置有導電通孔之場所。導電通孔381b連接配線380及第一配線360b。第一配線360b電性連接至設置於半導體晶片320之元件表面322之電極326b。導電通孔481b連接第二配線370及第一配線460b。第一配線460b電性連接至設置於半導體晶片420之元件表面422之電極426b。
導電通孔381a連接第三配線390及第一配線360a。第一配線360a電性連接至設置於半導體晶片320之元件表面322之電極326a。導電通孔481a連接第三配線390及第一配線460a。第一配線460a電性連接至設置於半導體晶片420之元件表面422之電極426a。其中,第三配線390形成為與第二配線370及配線380同層。參照圖30及圖33可知,第三配線390並未與第二配線370及配線380電性連接。
半導體晶片320之電極326a經由第一配線360a、導電通孔381a、第三配線390、導電通孔481a、第一配線460a電性連接至半導體晶片420之電極426a。如此一來,關於本發明之第三實施型態之半導體封裝300之結構中,單側表面具有電極之半導體晶片320及420以具有電極之表面為同向之方式並列配置,而另一方面同時能夠藉由配置於半導體晶片上方之配線而電性連接雙方之電極,進而能夠於單一個封裝內構成由雙半導體晶片製成之電路。因此,關於本發明之第三實施型態之半導體封裝300,能夠構成晶片間電性連接之模組(module),進而能夠實現高性能。
此外,第二配線370藉由較大口徑之導電通孔371連接至半導體晶片320。同樣地,第二配線470藉由較大口徑之導電通孔471連接至半導體晶片420。第二配線370及第二配線470由於能夠與第三配線390同層形成,故於構成上述半導體晶片320及半導體晶片420之電路的同時,還能夠降低自半導體晶片320、420之背表面至半導體封裝300之表面之熱阻抗。同樣地,亦能夠降低自半導體晶片320、420之配置有電極之元件表面至半導體封裝300之表面之熱阻抗。
以下將說明變形例。
以下將使用圖34至圖37說明第三實施型態之變形例。圖34至圖37為關於本發明之第三實施型態之變形例之半導體封裝之垂直剖面圖。圖34為位於圖30之B-B’線之垂直剖面圖。於圖34所示之C-C’線之水平剖面圖對應於圖30所示之俯視圖。其中,於圖30之配線380與第二配線370之間,及於第二配線370與第二配線470之間雖有間隙,但於本變形例中可由樹脂40a填充。圖35為位於圖30之D-D’線之垂直剖面圖,且對應於圖37。而且,圖35至圖37為繪示第三實施型態之變形例之製造流程之圖。自表示第三實施型態之圖33,再以圖35、圖36及圖37之順序,表示形成第三實施型態之變形例之流程。
以下將說明第三實施型態之變形例之製造方法。首先,於第三實施型態之半導體封裝300之上表面填充樹脂40a(參照圖35)。樹脂40a與樹脂40同樣亦可使用非感光性樹脂或感光性樹脂。參照圖35時,以覆蓋第二配線370及第三配線390之各自的側表面及上表面之方式填充樹脂40a。雖於圖35中未繪示,亦藉由樹脂40a覆蓋第二配線470及配線380之各自的側表面及上表面。
接下來,於樹脂40a形成開口部,以露出第二配線370之上表面之一部分或全部(參照圖36)。其中,由於第三配線390之上表面並未形成開口部,故第三配線390維持埋設於樹脂40a之狀態。
接下來,於先前形成於樹脂40a之開口部及樹脂40a之上表面形成第四配線372(參照圖37)。第四配線372可與第一實施型態中之第二配線70之形成方法中所說明之方法相同,藉由鍍覆法填充鍍覆銅材料而形成。雖於圖35至圖37中並未繪示,但亦可藉由與上述第四配線372之形成方法相同的方法形成第四配線472及第四配線382b。
圖34及圖37所示之變形例之特徵之一,為關於本發明之第三實施型態之半導體封裝300中於第二配線370、第二配線470及配線380之上配置第四配線372、472及382b。本發明之第三實施型態中之變形例,藉由具有上述結構,而能夠比第三實施型態更增加自半導體晶片320及420之背表面至半導體封裝之上表面之容許電流。因此,能夠允許流通更多電流,故能夠防止因過電流而造成之熔融斷路。
接下來,將使用圖38及圖39說明關於本發明之第三實施型態之半導體封裝之其他變形例。
圖38及圖39為本發明之第三實施型態之其他變形例之垂直剖面圖。圖38為位於圖30之B-B’線之垂直剖面圖,於圖38所示之C-C’線之水平剖面圖對應於圖30所示之俯視圖。其中,於圖30之配線380與第二配線370之間,及於第二配線370與第二配線470之間雖有間隙,但於本變形例中可由樹脂40a填充。圖39為位於圖30之D-D’線之垂直剖面圖,且對應於圖33。圖38及圖39所示之其他變形例,自上述第三實施型態之變形例,更於第一配線360b及第一配線460b之下側形成第五配線361b及第五配線461b。第五配線361b、第五配線461b及樹脂40b之材料及形成方法,與上述之變形例相同。
圖38及圖39所示之其他變形例,藉由具有上述結構,而能夠比第三實施型態更增加自半導體晶片320及420之配置有電極之元件表面至半導體封裝之下表面之容許電流。因此,能夠允許流通更多電流,故能夠防止因過電流而造成之熔融斷路。
以上,使用圖1至圖39說明關於本發明之實施型態及其變形例。然而,本發明並非限定於上述之實施型態等型態,亦能夠在未脫離要旨之範圍予以適當變更。
11、12‧‧‧支撐板
13‧‧‧光阻件
14、15‧‧‧抗鍍件
16‧‧‧臨時固定材
17‧‧‧固定材
20、320、420‧‧‧半導體晶片
20’‧‧‧虛線
22、322、422‧‧‧元件表面
24‧‧‧背表面
26、326a、326b、426a、426b‧‧‧電極
40、40a、40b‧‧‧樹脂
41、42、43、44、45、46、47‧‧‧開口部
60、360a、360b、460a、460b‧‧‧第一配線
63、64、71、72、73a、73b、73c、73d、74、81、371、381a、381b、471、481a、481b‧‧‧導電通孔
70、370、470‧‧‧第二配線
75a、75b、75c、75d、77a、77b、77c、77d‧‧‧導電通孔非形成部
80‧‧‧配線
100、200、300‧‧‧半導體封裝
361b、461b‧‧‧第五配線
372、382b、472‧‧‧第四配線
380‧‧‧配線
390‧‧‧第三配線
13‧‧‧光阻件
14、15‧‧‧抗鍍件
16‧‧‧臨時固定材
17‧‧‧固定材
20、320、420‧‧‧半導體晶片
20’‧‧‧虛線
22、322、422‧‧‧元件表面
24‧‧‧背表面
26、326a、326b、426a、426b‧‧‧電極
40、40a、40b‧‧‧樹脂
41、42、43、44、45、46、47‧‧‧開口部
60、360a、360b、460a、460b‧‧‧第一配線
63、64、71、72、73a、73b、73c、73d、74、81、371、381a、381b、471、481a、481b‧‧‧導電通孔
70、370、470‧‧‧第二配線
75a、75b、75c、75d、77a、77b、77c、77d‧‧‧導電通孔非形成部
80‧‧‧配線
100、200、300‧‧‧半導體封裝
361b、461b‧‧‧第五配線
372、382b、472‧‧‧第四配線
380‧‧‧配線
390‧‧‧第三配線
圖1為關於本發明之第一實施型態之半導體封裝之概略圖。 圖2為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖3為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖4為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖5為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖6為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖7為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖8為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖9為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖10為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖11為繪示關於本發明之第一實施型態之半導體封裝之製造流程之剖面圖。 圖12為關於本發明之第一實施型態之半導體封裝之剖面圖。 圖13為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖14為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖15為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖16為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖17為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖18為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖19為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖20為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖21為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖22為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖23為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖24為繪示關於本發明之第二實施型態之半導體封裝之製造流程之剖面圖。 圖25為關於本發明之第二實施型態之半導體封裝之剖面圖。 圖26A為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例1之水平剖面圖。 圖26B為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例1之垂直剖面圖。 圖27A為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例2之水平剖面圖。 圖27B為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例2之垂直剖面圖。 圖28A為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例3之水平剖面圖。 圖28B為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例3之垂直剖面圖。 圖29A為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例4之水平剖面圖。 圖29B為繪示關於本發明之第一實施型態及第二實施型態之半導體封裝之變形例4之垂直剖面圖。 圖30為關於本發明之第三實施型態之半導體封裝之水平剖面圖。 圖31為關於本發明之第三實施型態之半導體封裝之垂直剖面圖。 圖32為關於本發明之第三實施型態之半導體封裝之垂直剖面圖。 圖33為關於本發明之第三實施型態之半導體封裝之垂直剖面圖。 圖34為繪示關於本發明之第三實施型態之半導體封裝之變形例之垂直剖面圖。 圖35為繪示關於本發明之第三實施型態之半導體封裝之變形例之製造流程之垂直剖面圖。 圖36為繪示關於本發明之第三實施型態之半導體封裝之變形例之製造流程之垂直剖面圖。 圖37為繪示關於本發明之第三實施型態之半導體封裝之變形例之垂直剖面圖。 圖38為繪示關於本發明之第三實施型態之半導體封裝之其他變形例之垂直剖面圖。 圖39為繪示關於本發明之第三實施型態之半導體封裝之其他變形例之垂直剖面圖。
20‧‧‧半導體晶片
22‧‧‧元件表面
24‧‧‧背表面
26‧‧‧電極
40‧‧‧樹脂
60‧‧‧第一配線
71、81‧‧‧導電通孔
70‧‧‧第二配線
80‧‧‧配線
100‧‧‧半導體封裝
Claims (11)
- 一種半導體封裝,包括:一半導體晶片,具有配置有一電極之一元件表面及相反於該元件表面之一背表面,一樹脂覆蓋該半導體晶片;一第一配線,直接連接至該元件表面,或者經由配置於該樹脂之一第一開口部連接至該元件表面;以及一第二配線,經由配置於該樹脂之至少一第二開口部連接至該背表面。
- 一種半導體封裝,包括:多個半導體晶片,各該半導體晶片具有配置有一電極之一元件表面及相反於該元件表面之一背表面,一樹脂覆蓋該些半導體晶片;一第一配線,直接連接至該些元件表面,或者經由配置於該樹脂之一第一開口部連接至該些元件表面;一第二配線,經由配置於該樹脂之至少一第二開口部連接至該些背表面;以及一第三配線,設置於配置有該第二配線之該樹脂之層體,且經由配置於該樹脂之多個第三開口部電性連接至該第一配線,該第三配線電性連接該些半導體晶片中之相異之該些半導體晶片之該些電極。
- 如請求項1或2所述之半導體封裝,其中該第一配線包括依序堆疊金(Au)、鎳(Ni)及銅(Cu)之構造。
- 如請求項1或2所述之半導體封裝,其中該第二配線包括堆疊障壁金屬(barrier metal)及銅之構造。
- 如請求項1或2所述之半導體封裝,其中該至少一第二開口部之配置數量為多個。
- 一種半導體封裝之製造方法,包括:令一半導體晶片載置於一固定材之上,其中該半導體晶片之配置有一電極之一元件表面朝上且相反於該元件表面之一背表面朝下;於該固定材上填充一第一樹脂以埋設該半導體晶片;於該第一樹脂形成露出該元件表面之一第一開口部;於該元件表面上以鍍覆法(plating method)形成一第一配線;去除該固定材;於該背表面及該第一樹脂上填充一第二樹脂;於該第二樹脂形成露出該背表面之一第二開口部;於該第二樹脂上形成一抗鍍件(plating resist);以及於該背表面上以鍍覆法形成一第二配線。
- 一種半導體封裝之製造方法,包括:令多個半導體晶片載置於一固定材之上,其中各該半導體晶片之配置有一電極之一元件表面朝上且相反於該元件表面之一背表面朝下;於該固定材上填充一第一樹脂以埋設該些半導體晶片;於該第一樹脂形成露出該些元件表面之一第一開口部;於該些元件表面上以鍍覆法形成一第一配線;去除該固定材;於該些背表面及該第一樹脂上填充一第二樹脂;於該第二樹脂形成露出該些背表面之一第二開口部及露出該第一配線之一第三開口部;於該第二樹脂上形成一抗鍍件;以及於該第二開口部、該第三開口部及該第二樹脂上鍍銅,以於該第二開口部及該第二樹脂上形成一第二配線,且於該第三開口部及該第二樹脂上形成一第三配線,該第三配線電性連接該些半導體晶片中之相異之該些半導體晶片之該些電極。
- 一種半導體封裝之製造方法,包括:於一支撐板塗布一感光性阻件;於該感光性阻件之一部分開設一開口;於該開口以鍍覆法形成一第一配線;準備一半導體晶片,其具有配置有一電極之一元件表面及相反於該元件表面之一背表面,以連接該第一配線及該電極之方式覆晶(flip chip)連接該半導體晶片至該第一配線上;於該支撐板上填充一樹脂以埋設該半導體晶片及該第一配線;於該樹脂形成露出該背表面之一開口部;於該樹脂上形成一抗鍍件;以及於該背表面上以鍍覆法形成一第二配線。
- 一種半導體封裝之製造方法,包括:於一支撐板塗布一感光性阻件;於該感光性阻件之一部分開設一開口;於該開口以鍍覆法形成一第一配線;準備多個半導體晶片,各該半導體晶片具有配置有一電極之一元件表面及相反於該元件表面之一背表面,以連接該第一配線及該些電極之方式覆晶連接該些半導體晶片至該第一配線上;於該支撐板上填充一樹脂以埋設該些半導體晶片及該第一配線;於該樹脂形成露出該些背表面之一開口部及露出該第一配線之一開口部;於該樹脂上形成一抗鍍件;以及於露出該些背表面之該開口部、露出該第一配線之該開口部及該樹脂上鍍銅,以於露出該些背表面之該開口部及該樹脂上形成一第二配線,且於露出該第一配線之該開口部及該樹脂上形成一第三配線,該第三配線電性連接該些半導體晶片中之相異之該些半導體晶片之該些電極。
- 如請求項8或9所述之半導體封裝之製造方法,其中形成該第一配線之步驟,包括於最下層實施鍍金,接下來實施鍍鎳,以及接下來實施鍍銅。
- 7、8或9所述之半導體封裝之製造方法,其中形成該第二配線之步驟,包括濺射(sputtering)障壁金屬,以及接下來實施鍍銅。
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