JP2016201468A - 半導体パッケージ及びその製造方法 - Google Patents
半導体パッケージ及びその製造方法 Download PDFInfo
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- JP2016201468A JP2016201468A JP2015080718A JP2015080718A JP2016201468A JP 2016201468 A JP2016201468 A JP 2016201468A JP 2015080718 A JP2015080718 A JP 2015080718A JP 2015080718 A JP2015080718 A JP 2015080718A JP 2016201468 A JP2016201468 A JP 2016201468A
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Abstract
【解決手段】 電極の配置された素子面と前記素子面に対向する裏面を有し、樹脂に覆われた半導体チップと、前記電極に直接又は前記樹脂に配置された第1開口部を介して接続される第1の配線と、前記樹脂に配置された第2開口部を介し、前記裏面と接続される第2の配線とを有する半導体パッケージを提供する。
【選択図】図12
Description
図1乃至図12を用いて、第1実施形態に係る半導体パッケージの構成及びその製造方法について説明する。
図1は、本発明の第1実施形態に係る半導体パッケージ100の全体構成を示す概略図である。半導体チップ20は、樹脂40の中に埋設されている。第2の配線70は、ビア(図示せず)を介して半導体チップ20の上面に接続される。また、第1の配線(図示せず)は半導体パッケージ100の下側に形成され、半導体チップ20の電極26(図示せず)に直接接続される。また、第1の配線と配線80は、ビアを介して電気的に接続される。
図2乃至12は、本発明の第1実施形態に係る半導体パッケージ100の製造過程を順に示した図であり、図1のI−I’線における断面図を示したものである。
次に、第2実施形態に係る半導体パッケージの構成及びその製造方法について説明する。なお、半導体パッケージの全体構造は、第1実施形態で説明した図1と同様である。
図13乃至25は、本発明の第1実施形態に係る半導体パッケージ100の製造過程を順に示した図であり、図1のI−I’線における断面図を示したものである。
第1実施形態及び第2実施形態では、樹脂46に半導体チップ20の形状に沿った矩形状の比較的大きな口径の開口部41又は46を開口して、めっき法によりビア71を形成した。ここで、フォトリソグラフィによるパターンニングで、メタルの分割パターニングを容易に実現することができるので、以下に示す分割パターニングを容易に形成することが可能となる。
図30乃至図33を用いて、第3実施形態に係る半導体パッケージの構成及びその製造方法について説明する。
以下に、図34乃至図37を用いて、第3実施形態の変形例を説明する。図34及び図37は、本発明の第3実施形態の変形例に係る半導体パッケージの垂直断面図である。図34は、図30のB−B’線における垂直断面図であり、図32に対応する。図35は、図30のD−D’線における垂直断面図であり、図33に対応する。また、図35及び図36は、第3実施形態の変形例の製造工程を示す図である。第3実施形態を示す図32から、図35、図36及び図37の順で、第3実施例の変形例が形成される過程を示している。
13:フォトレジスト
14、15:めっきレジスト
16:仮固定材
17:固定材
20、320、420:半導体チップ
22、322、422:素子面
24:裏面
26、326a、326b、426a、426b:電極
41、42、43、44、45、46、47:開口部
60、360a、360b、460a、460b:第1の配線
63、64、71、72、73a、73b、73c、73d、74、81、371、381a、381b、471、481a、481b:ビア
70、370、470:第2の配線
75a、75b、75c、77a、77b、77c:ビア非形成部
80:配線
100、200、300:半導体パッケージ
361b:第5の配線
372、472:第4の配線
380:配線
390:第3の配線
Claims (11)
- 電極の配置された素子面と前記素子面に対向する裏面を有し、樹脂に覆われた半導体チップと、
前記素子面に直接又は前記樹脂に配置された第1ビアを介して接続される第1の配線と、
前記樹脂に配置された第2開口部を介し、前記裏面と接続される第2の配線と
を有する半導体パッケージ。 - 電極の配置された素子面と前記素子面に対向する裏面を有し、樹脂に覆われた複数の半導体チップと、
前記素子面に直接又は前記樹脂に配置された第1開口部を介して接続される第1の配線と、
前記樹脂に配置された第2開口部を介し、前記裏面と接続される第2の配線と、
前記第2の配線が配置された前記樹脂の層に、前記樹脂に配置された複数の第3開口部を介して前記第1の配線と電気的に接続される第3の配線とを有し、
前記第3の配線は、前記複数の半導体チップのうち互いに異なる半導体チップの電極を電気的に接続することを特徴とする、半導体パッケージ。 - 前記第1の配線は、Au、Ni及びCuが順に積層された構造を有する、請求項1又は2に記載の半導体パッケージ。
- 前記第2の配線は、バリアメタルとCuが積層された構造を有する、請求項1又は2に記載の半導体パッケージ。
- 前記第2開口部を複数配置することを特徴とする、請求項1又は2に記載の半導体パッケージ。
- 半導体チップを、前記半導体チップの電極が配置された素子面を上に、前記素子面に対向する裏面を下にして、固定材の上に載置し、
前記固定材上に前記半導体チップを埋設するよう第1の樹脂を充填し、
前記第1の樹脂に前記素子面を露出する第1開口部を形成し、
前記素子面上に第1の配線をめっき法によって形成し、
前記固定材を除去し、
支持板上に前記第1の配線を下にして前記第1の樹脂に埋設された前記半導体チップを載置し、
前記裏面及び前記第1の樹脂上に、第2の樹脂を充填し、
前記第2の樹脂に前記裏面を露出する第2開口部を形成し、
前記第2の樹脂上にめっきレジストを形成し、
前記裏面上に第2の配線をめっき法によって形成する
半導体パッケージの製造方法。 - 複数の半導体チップを、前記複数の半導体チップの電極が配置された素子面を上に、前記素子面に対向する裏面を下にして、固定材の上に載置し、
前記固定材上に前記半導体チップを埋設するよう第1の樹脂を充填し、
前記第1の樹脂に前記素子面を露出する第1開口部を形成し、
前記素子面上に第1の配線をめっき法によって形成し、
前記固定材を除去し、
支持板上に前記第1の配線を下にして前記第1の樹脂に埋設された前記半導体チップを載置し、
前記裏面及び前記第1の樹脂上に、第2の樹脂を充填し、
前記第2の樹脂に、前記裏面を露出する第2開口部と、前記第1の配線を露出する第3開口部を形成し、
前記第2の樹脂上にめっきレジストを形成し、
前記第2開口部、前記第3開口部及び前記第2の樹脂上にCuをめっきすることによって、前記第2開口部及び前記第2の樹脂上に第2の配線を形成し、前記第3開口部及び前記第2の樹脂上に第3の配線を形成し、
前記第3の配線は、前記複数の半導体チップのうち互いに異なる半導体チップの電極を電気的に接続することを特徴とする、半導体パッケージの製造方法。 - 支持板に感光性レジストを塗布し、
前記感光性レジストの一部を開口し、
前記開口に第1の配線をめっき法によって形成し、
電極の配置された素子面と前記素子面に対向する裏面を有する半導体チップを、前記第1の配線上に、前記第1の配線と前記電極が接続するようフリップチップ接続し、
前記支持板上に、前記半導体チップ及び前記第1の配線を埋設するよう樹脂を充填し、
前記樹脂に前記裏面を露出する第2開口部を形成し、
前記第2の樹脂上にめっきレジストを形成し、
前記裏面上に第2の配線をめっき法によって形成する、半導体パッケージの製造方法。 - 支持板に感光性レジストを塗布し、
前記感光性レジストの一部を開口し、
前記開口に第1の配線をめっき法によって形成し、
電極の配置された素子面と前記素子面に対向する裏面を有する複数の半導体チップを、前記第1の配線上に、前記第1の配線と前記電極が接続するようフリップチップ接続し、
前記支持板上に、前記複数の半導体チップ及び前記第1の配線を埋設するよう樹脂を充填し、
前記樹脂に、前記裏面を露出する第2開口部と、前記第1の配線を露出する第3開口部を形成し、
前記樹脂上にめっきレジストを形成し、
前記第2開口部、前記第3開口部及び前記樹脂上にCuをめっきすることによって、前記第2開口部及び前記樹脂上に第2の配線を形成し、前記第3開口部及び前記樹脂上に第3の配線を形成し、
前記第3の配線は、前記複数の半導体チップのうち互いに異なる半導体チップの電極を電気的に接続することを特徴とする、半導体パッケージの製造方法。 - 前記第1の配線の形成は、最下層にAuめっきを実施し、次にNiめっきを実施し、次にCuめっきを施すことを特徴とする、請求項8又は9に記載の半導体パッケージの製造方法。
- 前記第2の配線の形成は、バリアメタルをスパッタリングし、次にCuめっきを施すことを特徴とする、請求項6乃至9のうちいずれか一項に記載の半導体パッケージの製造方法。
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KR102525389B1 (ko) | 2023-04-26 |
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JP6430883B2 (ja) | 2018-11-28 |
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