TW200814209A - Flip-chip interconnection with formed couplings - Google Patents

Flip-chip interconnection with formed couplings Download PDF

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Publication number
TW200814209A
TW200814209A TW096122747A TW96122747A TW200814209A TW 200814209 A TW200814209 A TW 200814209A TW 096122747 A TW096122747 A TW 096122747A TW 96122747 A TW96122747 A TW 96122747A TW 200814209 A TW200814209 A TW 200814209A
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TW
Taiwan
Prior art keywords
bump
coupling
electrical
contact
range
Prior art date
Application number
TW096122747A
Other languages
English (en)
Inventor
Wojtek Sudol
Martha Wilson
Original Assignee
Koninkl Philips Electronics Nv
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Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Publication of TW200814209A publication Critical patent/TW200814209A/zh

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200814209 九、發明說明： 【發明所屬之技術領域】 本系統係關於使用具有一成形電接點連接之一覆晶類型 之電互連之一互連方法及器件。 【先前技術】 積體電路（ic)技術之當前狀態係尺寸不斷減小而複雜度 不斷增加。隨著組件之密度增加，由於物理互連估有有： 表面區域之一顯著部分而減低此區域中定位電路之能力， 電耗接組件之系統變得非常關鍵。 已知-電互連技術，其中該互連之—部分係藉由一接觸 凸塊形成，而該互連之另一部分係藉由一接觸接點形成。 該接點有隸進行電連接之—方法。該凸塊亦提供進行電 連接之-方法’並亦具有—實f的高度以在連接基板之間 提供-實體分離。典型地，該凸塊產生於纖之表面上， 而該接點定位於聲學元件之底部。在製造程序朗，該凸 塊與接點相互接觸㈣成電互連。則丨用方式整體併入本 文=美國專利第6，G15,652號揭示—種類型之此—互連系統 ;負t該互連系統稱為關於安裝於一基板上之ic之「覆 晶j合」。β此典型互連系統減少與其他電互連系統相關ς 之些問題，但仍然佔用很多有效的表面區域，否則該等 有效表面區域可由電組件加以利用。當電互連係直接作用 於積體電路（例如特定應用積體電路（ASIC))時，此問題 係更加嚴重。 以引用方式整體併入本文中之PCT專利申請案 121832.doc 200814209 2004/052209揭示一系統’該系統將—ASIC電輪接至複數 #聲學元件用於形成一小型化的轉換器。在所示系統中， 該凸塊係電轉接至聲學元件或ASIC之一者，而該接點係電 搞接至該聲學元件或ASIC<另一者。此系統實現―小電封 裝，其（例如）可形成用以創建可用於經食管、腹腔鏡式以 及心内檢查之一超聲波轉換器。但'是’由於此等產品採取 直接在該聲學元件下面之單元電路之一間距匹配，所以需 _ 要進一步減低該間距。適當操作所需之當前混合信號asi= 耘序與電壓仍然限制該聲學元件與控制電路之進一步縮 減。例如，對於定位於一185 um間距陣列上之使用柱形凸 塊110之一覆晶互連系統丨〇〇(如圖丨所示）’由於此等凸塊， 大約40 /〇之該ASIC之區域係無法用於電路。電互連至該等 凸塊之接點或表面與該凸塊之接觸表面相比，係典型地較 大k向地棱跨接觸該凸塊之一表面。換言之，與該接點進 行電互連之凸塊表面係小於該接點上之一對應的接觸表 面0 【發明内容】 本系統之一目的係克服先前技術中之缺點及/或進行改 良。本系統之一目的係提供方法來減少使用晶片製造技術 之間距，例如，使用典型的ASIC技術可獲得。 依據本系統，一覆晶電耦接係形成於第一與第二電組件 之間。該耦接包含一凸塊以及一接點。該凸塊係電翁接至 第一電組件。該接點係電耦接至第二電組件。該接點係電 麵接至該凸塊之一對應的耦接表面並尺寸小於其。在一具 121832.doc 200814209 版貝轭例中，接點與凸塊可使用超聲波柱形凸塊接合程序 %柄接在一起Q ±r Vt 长另一具體實施例中，該接點與凸塊可使 用導電環氧樹脂電Mu該凸塊可綠形、球形 等0 丰同或另具體實施例中，該第一電組件可係一聲學 牛及/或忒第一電組件可係一 ASIC。該耦接可係呈現於 J於150 um之間距陣列中之複數個電耦揍之一者。 以下係况明性具體實施例之說明，其將結合以下圖式說 :表述以及進一步之特徵及優點。在以下說明中，目 的係說明而非限也{ k出之諸如特定架構、介面、技術等 :特疋：即係用於說明。但是熟悉此項技術人士應明白， 月離此等特疋細節之其他具體實施例仍應理解為屬於隨附 申請專利範圍之餘^ 乾可内。而且，為清晰起見，省略眾所周 知之器件、雷脸n +、丄 及方法之詳細說明，以便不模糊本系 之說明。 【實施方式】 圖2』不依據本系統之一具體實施例之一覆晶互連系統 200之一說明性齡 斷面圖。在此具體實施例t，一高方位凸 塊210顯示為一知； “ 柱形凸塊形式，在製造期間，其係電耦接 至電、/件（例如聲學元件250)之一解匹配層表面23〇σ該 ,"+何形式，包含球形、柱形或可適於應用之其他 形狀。該聲學开/生π y么 件可係一種產生可用於一超聲波轉換器應 用中之超聲波能發射之一聲學元件之類型。 ^ 依據本系統之一具體貴施例之圖2中顯示之說明 nmiAoc 200814209 性覆晶互連系統200之詳述的斷面區域區段290。該凸塊 210可使用任何製造程序加以製造，該等技術例如電鍍、 加工、成形、電子平版印刷術、導線接合或可適於應用之 任何其他製造程序。在一應用中，該凸塊210之高度可係 / 在50至150 um之範圍內，如100 um高；並具有與該聲學元 件250電耦接之一接觸表面214,且該表面具有50至120 um 之範圍内之一直徑，例如70 um。該凸塊210之高度有助於 在連接基板（例如聲學元件250與ASIC 260)之間提供一實 W 體分離。 依據本系統之一具體實施例，——1C(例如ASIC 260)具有 接觸接點220，該等接觸接點220透過其之一接觸表面224 電耦接至ASIC 260。該電耦接可透過ASIC 260之一接觸金 屬化層265或用於在接觸接點220與該ASIC 260之間提供電 互連之任何其他系統得以提供。在一具體實施例中，該等 接點220可具有10至70 um之範圍内之一直徑225(例如20 ^ um之直徑），以及1至30 um之範圍内之高度（例如15 um之 高度）。該等接點220可藉由任何成形及/或沈積程序形成， 包含電解電鍍、濺鍍、光沈積或可適於應甩之其他系統。 在一具體實施例中，該等接點220可利用金之電解電鍍簡 ’ 單形成，如同可使用低成本之冶金技術輕易獲得。 依據本系統，與該凸塊210之一接觸表面21 5相比，形成 之該接點220具有一小直徑225。例如，該接觸表面21 5可 具有40至80 um之範圍内之一直徑21 8，例如5〇11111之直 徑。藉由在ASIC 260上形成一相對小的直徑接點220，與 121832.doc 200814209 先前系統相比，該ASIC表面區域之較大部分可用於電路。 例如，互連之本系統可適於應用於15〇山^或更小之細密間 距陣列中。在另一具體實施例中，在該凸塊2 i 〇接觸表面 215與該接點220接觸表面228之間的電耦接可使用低溫以 及壓力接合技術（例如超聲波柱形凸塊接合）獲得。此技術 具有額外的優點，由於在接合，表面之間（例如，凸塊與接 點之間）利用低壓，該接點220下面之該ASIC 26〇之區域 (例如該ASIC 260之頂部金屬化層265下面）可供電路利 用，並因此，與先前系統相比，可導致更多可利用之該 ASIC之區域。在另一具體實施例中，該接點與該凸塊 210可使用導電環氧樹脂電耦接在一起。 學凡件250可係任何類型及組態，包 3-D超聲波成像應用及/或矩陣轉換器 之一組態。 一此外γ應很容易瞭解，雖然在說明性具體實施例中，顯 不二個聲學元件25〇與三個互連系統（例如，凸塊與接 點220)，但取決於一所需應用可使用更多或更少。該等聲 ，包含有助於諸如可用於 換器組態之3維（3-D)成像 當然，應瞭解，以上具體實施例或程序之任一者可依據 本系、.4與-或多個其他具體實施例或㈣相結合來提供更 進—步之改良。
施例以特定細節加 谓至任何特定之具體.實施何或具體 雖然本系統已參考其特定範例性具 以說明，亦應瞭解在不背離以下申 121832.doc 200814209 請專利範葛所提出之本系統之廣泛及所期望之精神及範疇 之情況下，熟悉此項技術人士可作出多種修改及可替換具 體實施例。因此，說明及等圖式係認為一說明性方式而非 意欲限制隨附申請專利範圍之範疇。 在說明該等隨附申請專利範圍時，應瞭解： a) 單詞「包含」並不排除_給定請求項中列出之此等元 件或動作之外之其他元件或動作之存在； b) 凡件W之單詞「_」或「一個」不排除複數個此類元 件之存在； c) 睛求項中任何參考符號不限制其範疇； 數個「構件」可藉由實施之結構或功能之相同 硬體或軟體加以表示； ' ' e)任何揭示之元件可包合#驊八 匕3硬體邛分（例如，包含離散之及 積體電路）、軟體部分（例 丄 、例如電私私式設計）以及其任何組 j〇S^ ·
肩體部分可包含類比與數位部分之—者或兩者； 之:)任何揭示之器件或其部分可組合在一起或分離成其4 之邛分，除非另外特別說明；以及 除非明確指示。 h)未意欲要求動作或步驟之特定順序， 【圖式簡單說明】 於說明性目的而不表示 同圖式中的相同參考數 應清楚瞭解，所包含之圖式係用 本系統之範疇。在該等附圖令，不 字指定類似的元件。 圖】顯示一先前技術 覆 晶互連系統 12i832.doc 200814209 圖2顯示依據本系統之一具體實施例之一覆晶互連之一 說明性斷面圖；以及 圖3顯示依據本系統之一具體實施例之圖2寸顯示之說明 性覆晶互連系統200之詳述的斷面區域區段290。 【主要元件符號說明】 100 覆晶互連系統 110 柱形凸塊 200 覆晶互連系統
210 凸塊 214 第一電耦接表面/接觸表面 2 1 5 第二電耦接表面/接觸表面 220 接點 224 第一電搞接表面/接觸表面 228 第二電耦接表面 230 解匹配層表面 250 260 265 290 聲學元件/第一組件 ASIC/第二組件 接觸金屬化層/ASIC之頂部金屬化層 覆晶互連系統200之斷面區域區段 I21832.doc -12·

Claims (1)

  1. 200814209 十、申請專利範爵： 一種在第一與第二電組件（250、260)之間的覆晶電耦 接，該耦接包含： 一凸塊(210)，其包含第一與第二電|焉接表面（214、 215)，其中該凸塊（21 〇)之該第一耦接表面(214)係電耦接 至該第一電組件（250);以及 一接點（220)，其包含第一與第二電耦接表面（224、 22S)，其中該接點（22〇)之該第一耦接表面（224)係電耦接 至该第二電組件（26〇)，並且該揍點（220)之該第二電耦 接表面（228)係電耦接至該凸塊（21〇)之該第二電耦接表 面（215)並尺寸小於其。 2. 3. 4. 5. 如哨求項1之耦接，其中該凸塊（210)係一柱形凸塊。 如請求項1之耦接，其中該凸塊（2ϊ〇)係一球形凸塊。 如请求項1之耦接，其中該凸塊（210)係組態成具有50至 150 um之範圍内之一凸塊高度。
    如印求項1之耦接，其中該凸塊之該第一耦接表面（214) 具有50至12〇 um之範圍内之一直徑。 6. 如印求項1之权接，其中該接點（220)係組態成具有1〇至 70聰之範圍内之一直徑。 月求項1之耦接，其中該第一電組件（25〇)係一聲學元 件。 月求項1之耦接，其中該第二電組件（26〇)係一 ASic。 9·如清求項8之輕接，其中該ASIC係組態成具有定位於該 接點下，面之電路。 121832.doc 200814209 10·如請灰工斎’ 之、耦接’其中該耦接係組態成為小於150 Um 之間距陣列中複數個電耦接之一者。 U· 一種用於在第一盥第一 * J-電組件（250、260)之間形成覆晶 包 之方法，程序包含以下動作： 將一凸塊部分（210)耦接至該第一電組件(25〇); :接點部分（220)輕接至該第二電組件（26〇);以及 將该凸塊部分（21〇)辆接至該接點部分（22〇)，其中耦
    接至讓凸塊部分（2 i 〇)之該接點部分（22〇)之一表面（U^ 之尺寸係小於該凸塊部分（21〇)之一對應耦接表面（215) 之尺寸。 12·如凊求前之方法，其包含將該凸塊部分（㈣）形成為一 柱形凸塊部分之動作。 月求員11之方法，其包含形成該凸塊部分（2 10)之動 作，該凸塊部分具有5〇至150 um之範圍内之一凸塊高度 以及耦接至該第一電組件（25〇)並具有5〇至12〇 um之範圍 内之一直徑之一表面（214)。 14·如請求項11之方法，其包含形成具有10至70 um之範圍 内之一直徑之接點部分（22〇)之動作。 15 ·如明求項11之方法，其中使用低溫及低接合壓力耦接技 術執行將該凸塊部分（210)耦接至該接點部分（220)之動 作0 16.如請求項15之方法，其中該低溫與低接合壓力耦接技術 係超聲波柱形凸塊接合。 17·如請求項u之方法，其包含將該覆晶電耦接形成為在小 121832.doc 200814209
    於150 um之間距陣列内成形的複數値(電耦接之一者之動 作。 18.如請求項11之方法，其中使用導電環氧樹脂執行將該凸 塊部分（210)耦接至該接點部分（220)之動作。 121&32,doc
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US9180490B2 (en) 2012-05-22 2015-11-10 General Electric Company Ultrasound transducer and method for manufacturing an ultrasound transducer
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US6015652A (en) * 1998-02-27 2000-01-18 Lucent Technologies Inc. Manufacture of flip-chip device
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US6815252B2 (en) * 2000-03-10 2004-11-09 Chippac, Inc. Method of forming flip chip interconnection structure
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US20060116584A1 (en) * 2002-12-11 2006-06-01 Koninklijke Philips Electronic N.V. Miniaturized ultrasonic transducer
US7353056B2 (en) * 2003-03-06 2008-04-01 General Electric Company Optimized switching configurations for reconfigurable arrays of sensor elements
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US6849944B2 (en) * 2003-05-30 2005-02-01 Texas Instruments Incorporated Using a supporting structure to control collapse of a die towards a die pad during a reflow process for coupling the die to the die pad
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