TW200745858A - Unified memory and controller - Google Patents

Unified memory and controller

Info

Publication number
TW200745858A
TW200745858A TW095147127A TW95147127A TW200745858A TW 200745858 A TW200745858 A TW 200745858A TW 095147127 A TW095147127 A TW 095147127A TW 95147127 A TW95147127 A TW 95147127A TW 200745858 A TW200745858 A TW 200745858A
Authority
TW
Taiwan
Prior art keywords
address
bus
memory
volatile
data
Prior art date
Application number
TW095147127A
Other languages
English (en)
Inventor
Fong-Long Lin
Bing Yeh
Original Assignee
Silicon Storage Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Storage Tech Inc filed Critical Silicon Storage Tech Inc
Publication of TW200745858A publication Critical patent/TW200745858A/zh

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10Address translation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Memory System (AREA)
TW095147127A 2005-12-28 2006-12-15 Unified memory and controller TW200745858A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US75493705P 2005-12-28 2005-12-28
US11/637,420 US20070147115A1 (en) 2005-12-28 2006-12-11 Unified memory and controller

Publications (1)

Publication Number Publication Date
TW200745858A true TW200745858A (en) 2007-12-16

Family

ID=37951827

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095147127A TW200745858A (en) 2005-12-28 2006-12-15 Unified memory and controller

Country Status (5)

Country Link
US (1) US20070147115A1 (zh)
EP (1) EP1804156A3 (zh)
JP (1) JP2007183962A (zh)
KR (1) KR100797325B1 (zh)
TW (1) TW200745858A (zh)

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* Cited by examiner, † Cited by third party
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TWI814647B (zh) * 2022-11-24 2023-09-01 慧榮科技股份有限公司 執行主機命令的方法及電腦程式產品及裝置

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI814647B (zh) * 2022-11-24 2023-09-01 慧榮科技股份有限公司 執行主機命令的方法及電腦程式產品及裝置

Also Published As

Publication number Publication date
EP1804156A2 (en) 2007-07-04
JP2007183962A (ja) 2007-07-19
US20070147115A1 (en) 2007-06-28
KR20070070121A (ko) 2007-07-03
KR100797325B1 (ko) 2008-01-22
EP1804156A3 (en) 2007-11-21

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