TW200409197A - Method for manufacturing semiconductor device through use of mask material - Google Patents

Method for manufacturing semiconductor device through use of mask material Download PDF

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Publication number
TW200409197A
TW200409197A TW092124080A TW92124080A TW200409197A TW 200409197 A TW200409197 A TW 200409197A TW 092124080 A TW092124080 A TW 092124080A TW 92124080 A TW92124080 A TW 92124080A TW 200409197 A TW200409197 A TW 200409197A
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Taiwan
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film
mask
pattern
masking material
semiconductor device
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TW092124080A
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Takeshi Matsunuma
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Renesas Tech Corp
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
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    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

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Description

200409197 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置之製造方法，尤其是關於 微細圖案之形成方法之半導體裝置之製造方法。 【先前技術】 以往，已知曉將氧化矽膜、氮化矽膜多晶矽等用作為遮 罩材料，而對該遮罩材之正下方的被加工膜施以蝕刻的微 細圖案的形成方法。 【發明内容】 (發明所欲解決之問題） 但是，因為對被加工膜之遮罩材的蝕刻選擇比低，因此 在蝕刻被加工膜時，會產生遮罩材被削肩的情況。於是， 在該削肩量多的情況，如圖4所示，會有遮罩材之正下方 的被加工膜（多晶矽膜）3 3也發生削肩3 3 a的問題。又，圖 4中，被加工膜3 3係形成於基板3 1上形成的閘極絕緣膜 32上。 另外，遮罩材因為在蝕刻被加工膜後變得沒有需要，而 有除去的必要。但是，以往要不致削去被圖案處理過的被 加工膜，而僅選擇性除去遮罩材有困難。為此，會有被加 工膜3 3的膜厚發生改變的問題。 藉此，在以往之半導體裝置之製造方法中，會有引起圖 案的劣化的問題。 本發明係為了解決上述以往的課題而提出者，其目的在 於，提供可僅選擇性除去遮罩材而不致削去被加工膜的半 5 312/發明說明書(補件)/92-11 /92124080 200409197 導體裝置的製造方法。另外，本發明之又一目的在於 容易形成微細圖案。 (解決問題之手段） 本發明之半導體裝置之製造方法，其特徵為具備如 驟：於基板上形成被加工膜的步驟；於上述被加工膜 成遮罩材的步驟；於上述遮罩材上形成抗餘劑圖案的 驟；將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩 步驟； 使上述圖案處理過的上述遮罩材收縮的步驟； 將已收縮的上述遮罩材作為遮罩而圖案加工上述被 工膜的步驟；及 除去上述遮罩材的步驟。 【實施方式】 以下，參照圖式來說明本發明之實施形態。又，對 相同或相當部分則賦予相同的元件符號，並簡略或省 說明。 (實施形態1 ) 圖1為說明本發明之實施形態1之半導體裝置之製 法用的剖面圖。詳細而言，圖1為說明A S IC等之微細 極佈線的形成方法用的圖。 首先，如圖1 (a)所示，在作為基板1 1的石夕晶圓上 成5 n Hi膜厚的用作為閘極絕緣膜1 2的閘極氧化膜，而 極絕緣膜1 2上形成1 5 0 n m膜厚的用作為閘極佈線材3 的多晶矽膜。接著，在閘極佈線材料1 3上形成2 0 n m 312/發明說明書(補件)/92-11 /92124080 ，可 下步 上形 步 材的 加 圖中 略其 造方 的閘 ，形 在閘 f 13 膜厚 6 200409197 的用作為遮罩材1 4的釕（R u )膜。然後於遮 抗蝕劑圖案1 5。 接著，如圖1 ( b )所示，藉由將抗蝕劑圖 而異向性蚀刻遮罩材1 4，形成遮罩材圖案 Ιά刻如係由 ICP(Inductively Coupled P1 來進行，該蝕刻條件成為如下。
高頻功率：1 5 0 0 W (上部）/ 2 0 0 W (下部） 壓力：3 0 mT 氣體：〇2/Cl2=100/10sccm 接著，如圖1 ( c )所示，藉由等向性蝕刻遮 形成圖案寬度較遮罩材圖案1 4 a還要微、細έ 1 4 b。亦即，藉由等向性蝕刻以使遮罩材圖 (s h r i n k )或後退。該等向性蝕刻如係由1 C C 〇 u ρ 1 e d P 1 a s m a )餘刻裝置來進行’ #玄蚀刻 高頻功率：1 5 0 0 W (上部）/ 8 0 W (下部）
壓力：2 OmT 氣體：〇2/Cl2=160/20sccm 然後，如圖1 ( d )所示，除去抗#劑圖案 接著，如圖1 ( e )所示，藉由將遮罩材圖； 而異向性蝕刻閘極佈線材料1 3 ^ ^ 向性蝕刻如係由ECR蝕刻裝置來進行’該^ 下。 高頻功率：4 0 0 W (上部）/ 3 0 W (下部） 壓力：4mTorr 312/發明說明書(補件)/92-11 /92124080 罩材1 4上形成 案1 5作為遮罩 1 4 a。該異向性 a s m a )蚀刻裝置 罩材圖案1 4 a， ί勺遮罩材圖案 案1 4 a收縮 P( Inductively 條件成為如下。 15° 奪1 4 b作為遮罩 佈線1 3 a。該異 丨虫刻條件成為如 7 200409197 氣體：HBr/Cl2/〇2=70/30/50sccm 最後，如圖1(f)所示，藉由除去遮罩材圖案14b，於閘 極絕緣膜1 2上形成閘極佈線1 3 a。該遮罩材圖案1 4 b的除 去如係由降流灰化型拋光裝置來進行，該拋光條件成為如 下。
微波電力：1 4 0 0 W 壓力：2 T 〇 r r
氣體：〇2/N2=900/100sccm 溫度：2 0 0 °C 如上述說明，本實施形態中，係將金屬膜之釕膜形成作 為遮罩材。藉由將抗蝕劑圖案1 5作為遮罩的異向性蝕刻而 形成遮罩材圖案1 4 a後，藉由實施等向性蝕刻以使遮罩材 圖案1 4 a收縮，藉由將該已收縮的遮罩材圖案1 4 b作為遮 罩的異向性#刻而形成閘極佈線1 3 a。 根據本實施形態1，作為閘極佈線材料1 3的多晶矽膜， 相對於作為遮罩材1 4的釕膜具有高蝕刻選擇比，因此，可 防止遮罩材的削肩等的圖案劣化。又，作為遮罩材1 4的釕 膜的除去，對於閘極佈線材料（多晶矽膜）或閘極絕緣膜（氧 化膜）具有高選擇比。因此可容易選擇除去遮罩材圖案14b 而不致削去閘極佈線1 3 a。藉此，可防止閘極佈線1 3 a的 膜厚變化。據此，可容易形成所需的形狀的閘極佈線1 3 a。 另外，因為可容易進行遮罩材的收縮，容易獲得微細的 遮罩材圖案14b，因此將此遮罩材圖案作為遮罩可容易形 成微細圖案（微細閘極佈線1 3 a )。 8 312/發明說明書(補件)/92-11/92124080 200409197 又，本實施形態1中，雖作為遮罩材14而使用釕月 但並不限於此，也可使用如鎢（W )膜或氮化鈦（T i N )膜 屬膜。在此，在將鐵（W )膜用作為遮罩材1 4的情況， 將Η 2 0 2水溶液用於遮罩材的收縮或除去，可獲得與將 用作為遮罩的情況相同的效果。另外，在將氮化鈦膜 為遮罩材1 4的情況，藉由將Η 2 0 2水溶液用於遮罩材ί 縮或除去，可獲得與此等相同的效果。 另外，本實施形態1中，係在使遮罩材圖案收縮後 去抗蝕劑圖案1 5，但是，也可將順序相反。也就是說 藉由將抗蝕劑圖案1 5作為遮罩的蝕刻以形成遮罩材S 案，而除去抗蝕劑圖案1 5後，也可使遮罩材圖案收縮 情況，因為在收縮時遮罩材圖案上面也被收縮，因此 罩14的形成膜厚形成為如60nm的厚度。 (實施形態2 ) 圖2為說明本發明之實施形態2之半導體裝置之製 法用的剖面圖。詳細而言，圖2與圖1相同，為說明 等之微細的閘極佈線的形成方法用的圖。 首先，如圖2 ( a)所示，利用與前述實施形態1相同 法（參照圖1 ( a ))，在矽晶圓1 1上，形成閘極絕緣膜 閘極佈線材料1 3、作為遮罩材1 4的釕（R u )膜及抗蝕 案15。 接著，如圖2 ( b )所示，利用與實施形態1相同的方：¾ 照圖1 ( b ))，形成遮罩材圖案1 4 a。 接著，如圖2 ( c )所示，藉由等向性蝕刻抗蝕劑圖案 312/發明說明書(補件)/92-11 /92124080 的金 藉由 釕膜 用作 勺收 以除 ，在 0該 將遮 造方 ASIC 的方 12、 劑圖 (參 15 9 200409197 及遮罩材圖案1 4 a。藉此，將抗蝕劑圖案1 5及遮罩材圖案 1 4 a收縮或後退。該等向性I虫刻如係由I C P ( I n d u c t i v e 1 y C o u p 1 e d P 1 a s m a )姓刻裝置來進行，該钱刻條件成為如下。 高頻功率：1 5 0 0 W (上部）/ 5 0 W (下部）
壓力：5 OmT 氣體：0 2 / C 1 2 = 2 0 0 / 2 0 s c c m 然後，如圖2 ( d )所示，將已收縮的抗蝕劑圖案1 5 a及遮 罩材圖案1 4 b作為遮罩而藉由異向性蝕刻除去閘極佈線材 料1 3，形成閘極佈線1 3 a。該異向性I虫刻如係由E C R I虫刻 裝置來進行，該蝕刻條件成為如下。 高頻功率：4 0 0 W (上部）/ 3 0 W (下部） 壓力：4mTorr 氣體：HBr/Cl2/〇2=70/30/50sccm 最後，如圖2(e)所示，藉由除去遮罩材圖案15a與遮罩 材圖案1 4 b，於閘極絕緣膜1 2上形成閘極佈線1 3 a。該遮 罩材圖案1 5 a與遮罩材圖案1 4 b的除去如係由降流灰化型 拋光裝置來進行，該拋光條件成為如下。
微波功率：1 4 0 0 W 壓力：2 T 〇 r r 氣體：Ο 2 / N 2 = 9 Ο Ο / 1 Ο 0 s c c m
溫度：2 Ο 0 °C 如上述說明，本實施形態2中，藉由將抗蝕劑圖案1 5 作為遮罩的異向性蝕刻而形成遮罩材圖案1 4 a後，藉由實 施等向性蝕刻以使抗蝕劑圖案1 5與遮罩材圖案1 4 a收縮， 10 312/發明說明書(補件)/92-11/92124080 200409197 藉由將該已收縮的遮罩材圖案1 5 a及遮罩材圖案1 4 b作為 遮罩的異向性蝕刻而形成閘極佈線1 3 a。其後，同時除去 遮罩材圖案15a及遮罩材圖案14b。 根據本實施形態2，在閘極佈線1 3 a形成後，利用除去 屬遮罩材圖案1 4 b的釕膜的條件，可同時除去遮罩材圖案 1 4 b與抗蝕劑圖案1 5。 藉此，除可獲得實施形態1的效果外，還可獲得不需要 在將圖案改寫於釕膜上後僅除去抗蝕劑圖案1 5的步驟，而 可減少製造步驟數的效果。 (實施形態3 ) 圖3為說明本發明之實施形態3之半導體裝置之製造方 法用的剖面圖。詳細而言，圖3為說明A S I C或D R A Μ等之 記憶元件上之連接於金屬佈線之通孔的形成方法用的剖面 圖。 首先，如圖3 ( a )所示，在基板（省略圖示）上形成下層佈 線2 1，在下層佈線2 1上形成1 . 5 // m膜厚的用作為層間絕 緣膜2 2的氧化矽膜（例如，T E 0 S膜、B S G膜、B P S G膜等）。 接著，在層間絕緣膜2 2上形成3 0 n m膜厚的用作為遮罩材 2 4的釕膜。然後於遮罩材2 4上形成抗餘劑圖案2 5。 接著，如圖3 ( b )所示，藉由將抗蝕劑圖案2 5作為遮罩 而異向性蝕刻遮罩材2 4，形成遮罩材圖案2 4 a。該異向性 I虫刻如係由 I C P ( I n d u c t i v e 1 y C 〇 u p 1 e d P 1 a s m a ) I虫刻裝置 來進行，該餘刻條件成為如下。 高頻功率：1 5 0 0 W (上部）/ 2 0 0 W (下部） 11 312/發明說明書(補件)/92-11 /92124080 200409197 壓力：3 0 m Τ 氣體：〇2/Cl2=100/10sccm 接著，如圖3 ( c )所示，藉由異向性14刻抗#劑圖案2 5 與遮罩材圖案2 4 a，形成從層間絕緣膜2 2的表面到達下層 佈線2 1的通孔2 6。該異向性蝕刻如係由E C R蝕刻裝置來 進行，該#刻條件成為如下。 高頻功率：1 7 0 0 W (上部）/ 7 0 0 W (下部） 壓力：4mTorr 氣體：C4F8/Ar/CO=25/200/20sccm 最後，如圖3 ( d )所示，藉由除去抗蝕劑圖案2 5與遮罩 材圖案2 4 a，於層間絕緣膜2 2内形成聯繫下層佈線21的 通孔2 6。該抗蝕劑圖案2 5與遮罩材圖案2 4 a的除去如係 由降流灰化型拋光裝置來進行，該拋光條件成為如下。
微波功率：1 4 0 0 W 壓力：2 Τ 〇 r r 氣體：〇2/N2=900/100sccm
溫度：2 0 0 °C 如上述說明，本實施形態3中，藉由將抗蝕劑圖案2 5 作為遮罩的異向性蝕刻而形成遮罩材圖案2 4 a後，藉由實 施將抗蝕劑圖案2 5與遮罩材圖案2 4 a作為遮罩的異向性蝕 刻，而於層間絕緣膜2 2内形成聯繫下層佈線2 1的通孔 26。其後，除去遮罩材圖案24a。 根據本實施形態3，作為遮罩材1 4的釕膜的除去，對於 層間絕緣膜、金屬材料及基板材料具有高選擇比。因此可 12 312/發明說明書(補件)/92-11 /92124080 200409197 容易選擇除去遮罩材圖案2 4 a，而不致削去層間絕緣膜 2 2、下層佈線2 1及基板。尤其是，藉由拋光乾式除去釕膜， 即使在類似佈線的金屬材料曝露於基板表面，仍無類似濕 式餘刻時的造成金屬材料的炫化的情況。藉此，可容易形 成所需形狀的通孔2 6，而不致削去層間絕緣膜及下層佈 線，亦即無圖案的劣化。 另外，本實施形態3中，在通孔2 6形成後，利用除去 遮罩材圖案2 4 a的條件，可同時除去遮罩材圖案2 4 a與抗 蝕劑圖案2 5。藉此，可獲得不需要在將圖案改寫於釕膜上 後僅除去抗蝕劑圖案2 5的步驟，而可減少製造步驟數的效 果。 又，本實施形態3中，說明了聯繫於下層佈線21的通 孔的形成方法，但是，本發明也同樣適用於聯繫於基板的 通孔的形成。該情況，因為可將濕式蝕刻用於光罩材的除 去，因此可由釕膜以外的金屬膜之鎢膜及氮化鈦膜來形成 作為光罩材。鐵膜的除去可使用H2O2水溶液，而氮化鈦膜 的除去可使用H2SO4水溶液。 另外，雖然製造步驟數有增加，如實施形態1般，也可 在形成遮罩材圖案2 4 a後，僅除去抗蝕劑圖案2 5，而將遮 罩材圖案2 4 a作為遮罩形成通孔2 6。 (發明效果） 根據本發明，可選擇性除去遮罩材而不致削去被加工 膜。另夕卜，根據本發明，可容易形成微細圖案。 【圖式簡單說明】 13 312/發明說明書(補件)/92-11 /92124080 200409197 圖1 ( a )〜（f )為說明本發明之實施形態1之半導體裝置 之製造方法用的剖面圖。 圖2 ( a )〜（e )為說明本發明之實施形態2之半導體裝置 之製造方法用的剖面圖。 圖3 ( a )〜（d )為說明本發明之實施形態3之半導體裝置 之製造方法用的剖面圖。 圖4為說明以往之半導體裝置之製造方法的問題用的剖 面圖。 (元件符號說明） 11 基板（矽晶圓） 12 閘極絕緣膜（閘極氧化膜） 13 閘極佈線材料（多晶矽膜） 13a 閘極佈線 14 遮罩材（釕膜） 14a 遮罩材圖案 14b 遮罩材圖案 15 抗蝕劑圖案 2 1 下層佈線 22 層間絕緣膜（氧化矽膜） 24 遮罩材（釕膜） 24a 遮罩材圖案 25 抗蝕劑圖案 2 6 通孔 14 312/發明說明書(補件)/92-11 /92124080

Claims (1)

  1. 200409197 拾、申請專利範圍： 1. 一種半導體裝置之製造方法，其特徵為具備如下步 驟： 於基板上形成被加工膜的步驟； 於上述被加工膜上形成遮罩材的步驟； 於上述遮罩材上形成抗蝕劑圖案的步驟； 將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩材的 步驟； 使上述圖案處理過的上述遮罩材收縮的步驟； 將已收縮的上述遮罩材作為遮罩而圖案加工上述被加 工膜的步驟；及 除去上述遮罩材的步驟。 2. 如申請專利範圍第1項之半導體裝置之製造方法，其 中，以金屬膜來形成上述遮罩材。 3 .如申請專利範圍第2項之半導體裝置之製造方法，其 中： 以釕膜來形成上述遮罩材； 使用含氧的電漿來除去上述遮罩材，同時除去上述抗蝕 劑圖案。 4. 一種半導體裝置之製造方法，其特徵為具備如下步 驟： 於基板上形成被加工膜的步驟； 於上述被加工膜上形成作為遮罩材的釕膜的步驟； 於上述遮罩材上形成抗蝕劑圖案的步驟； 15 312/發明說明書(補件)/92-11/92124080 200409197 將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩材的 步驟； 將已圖案處理的上述遮罩材作為遮罩而圖案加工上述 被加工膜的步驟；及 除去上述遮罩材的步驟。 5 .如申請專利範圍第4項之半導體裝置之製造方法，其 中，使用含氧的電漿來除去上述遮罩材，同時除去上述抗 I虫劑圖案。 6 .如申請專利範圍第5項之半導體裝置之製造方法，其 中，在金屬材料曝露於上述基板上的狀態，除去上述遮罩 材。 16 312/發明說明書(補件)/92-11 /92124080
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US9075316B2 (en) 2013-11-15 2015-07-07 Globalfoundries Inc. EUV mask for use during EUV photolithography processes
US10950444B2 (en) * 2018-01-30 2021-03-16 Tokyo Electron Limited Metal hard mask layers for processing of microelectronic workpieces
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