TW200409197A - Method for manufacturing semiconductor device through use of mask material - Google Patents

Method for manufacturing semiconductor device through use of mask material Download PDF

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Publication number
TW200409197A
TW200409197A TW092124080A TW92124080A TW200409197A TW 200409197 A TW200409197 A TW 200409197A TW 092124080 A TW092124080 A TW 092124080A TW 92124080 A TW92124080 A TW 92124080A TW 200409197 A TW200409197 A TW 200409197A
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Taiwan
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film
mask
pattern
masking material
semiconductor device
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TW092124080A
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Chinese (zh)
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Takeshi Matsunuma
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Renesas Tech Corp
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Publication of TW200409197A publication Critical patent/TW200409197A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

A gate oxide film is formed on a substrate. A polysilicon film is formed on the gate oxide film. A ruthenium film is formed as a mask material on the polysilicon film. A resist pattern is formed on the ruthenium film. After the ruthenium film is patterned using the resist pattern as a mask, a patterned ruthenium film is shrunk. After the polysilicon film is patterned using a shrunk ruthenium film, the shrunk ruthenium film is removed.

Description

200409197 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體裝置之製造方法，尤其是關於 微細圖案之形成方法之半導體裝置之製造方法。 【先前技術】 以往，已知曉將氧化矽膜、氮化矽膜多晶矽等用作為遮 罩材料，而對該遮罩材之正下方的被加工膜施以蝕刻的微 細圖案的形成方法。 【發明内容】 (發明所欲解決之問題） 但是，因為對被加工膜之遮罩材的蝕刻選擇比低，因此 在蝕刻被加工膜時，會產生遮罩材被削肩的情況。於是， 在該削肩量多的情況，如圖4所示，會有遮罩材之正下方 的被加工膜（多晶矽膜）3 3也發生削肩3 3 a的問題。又，圖 4中，被加工膜3 3係形成於基板3 1上形成的閘極絕緣膜 32上。 另外，遮罩材因為在蝕刻被加工膜後變得沒有需要，而 有除去的必要。但是，以往要不致削去被圖案處理過的被 加工膜，而僅選擇性除去遮罩材有困難。為此，會有被加 工膜3 3的膜厚發生改變的問題。 藉此，在以往之半導體裝置之製造方法中，會有引起圖 案的劣化的問題。 本發明係為了解決上述以往的課題而提出者，其目的在 於，提供可僅選擇性除去遮罩材而不致削去被加工膜的半 5 312/發明說明書(補件)/92-11 /92124080 200409197 導體裝置的製造方法。另外，本發明之又一目的在於 容易形成微細圖案。 (解決問題之手段） 本發明之半導體裝置之製造方法，其特徵為具備如 驟：於基板上形成被加工膜的步驟；於上述被加工膜 成遮罩材的步驟；於上述遮罩材上形成抗餘劑圖案的 驟；將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩 步驟； 使上述圖案處理過的上述遮罩材收縮的步驟； 將已收縮的上述遮罩材作為遮罩而圖案加工上述被 工膜的步驟；及 除去上述遮罩材的步驟。 【實施方式】 以下，參照圖式來說明本發明之實施形態。又，對 相同或相當部分則賦予相同的元件符號，並簡略或省 說明。 (實施形態1 ) 圖1為說明本發明之實施形態1之半導體裝置之製 法用的剖面圖。詳細而言，圖1為說明A S IC等之微細 極佈線的形成方法用的圖。 首先，如圖1 (a)所示，在作為基板1 1的石夕晶圓上 成5 n Hi膜厚的用作為閘極絕緣膜1 2的閘極氧化膜，而 極絕緣膜1 2上形成1 5 0 n m膜厚的用作為閘極佈線材3 的多晶矽膜。接著，在閘極佈線材料1 3上形成2 0 n m 312/發明說明書(補件)/92-11 /92124080 ，可 下步 上形 步 材的 加 圖中 略其 造方 的閘 ，形 在閘 f 13 膜厚 6 200409197 的用作為遮罩材1 4的釕（R u )膜。然後於遮 抗蝕劑圖案1 5。 接著，如圖1 ( b )所示，藉由將抗蝕劑圖 而異向性蚀刻遮罩材1 4，形成遮罩材圖案 Ιά刻如係由 ICP(Inductively Coupled P1 來進行，該蝕刻條件成為如下。200409197 (1) Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device with a method for forming a fine pattern. [Prior Art] Conventionally, a method for forming a fine pattern using silicon oxide film, silicon nitride film, polycrystalline silicon, or the like as a mask material and etching the processed film directly below the mask material has been known. [Summary of the Invention] (Problems to be Solved by the Invention) However, since the etching selection ratio of the masking material of the processed film is low, the masking material may be shaved when the processed film is etched. Therefore, in the case where the amount of shaving is large, as shown in FIG. 4, there is a problem that the film 3 (polycrystalline silicon film) 3 3 directly under the mask material also has a shaving 3 3 a. In FIG. 4, the processed film 33 is formed on the gate insulating film 32 formed on the substrate 31. In addition, since the masking material becomes unnecessary after etching the film to be processed, it is necessary to remove it. However, conventionally, it has been difficult to selectively remove only the masking material without removing the processed film that has been patterned. For this reason, there is a problem that the film thickness of the processed film 33 changes. Therefore, in the conventional method of manufacturing a semiconductor device, there is a problem that the pattern is deteriorated. The present invention was proposed by the present invention in order to solve the above-mentioned conventional problems, and an object thereof is to provide a half 5 312 / Invention Specification (Supplement) / 92-11 / 92124080 which can selectively remove only a masking material without removing the processed film 200409197 Manufacturing method of conductor device. It is another object of the present invention to easily form a fine pattern. (Means for Solving the Problems) The method for manufacturing a semiconductor device of the present invention is characterized by including the steps of: forming a processed film on a substrate; forming a masking material on the processed film; and forming a masking material on the masking material. The step of forming a resist pattern; using the resist pattern as a mask to pattern the mask step; shrinking the pattern-treated mask material; and shrinking the mask material as a mask The step of patterning the work film; and the step of removing the masking material. [Embodiment] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, the same or corresponding parts are given the same component symbols, and explanations are omitted or omitted. (Embodiment 1) Fig. 1 is a sectional view for explaining a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention. Specifically, FIG. 1 is a diagram for explaining a method for forming a fine wiring such as an AS IC. First, as shown in FIG. 1 (a), a gate oxide film serving as the gate insulating film 12 is formed on the Shi Xi wafer as the substrate 11 with a thickness of 5 n Hi, and the electrode insulating film 12 is formed on the wafer. A polycrystalline silicon film serving as the gate wiring material 3 was formed to a thickness of 150 nm. Next, a 20 nm 312 / Invention Specification (Supplement) / 92-11 / 92124080 is formed on the gate wiring material 13, and the gate can be omitted in the figure of the shape of the gate, which is shaped in the gate f. 13 A ruthenium (R u) film with a film thickness of 6 200409197 used as a masking material 1 4. Then cover the resist pattern 15. Next, as shown in FIG. 1 (b), the masking material 14 is anisotropically etched with a resist pattern to form a masking material pattern. The etching conditions are performed by ICP (Inductively Coupled P1), and the etching conditions are as follows. Become as follows.

高頻功率：1 5 0 0 W (上部）/ 2 0 0 W (下部） 壓力：3 0 mT 氣體：〇2/Cl2=100/10sccm 接著，如圖1 ( c )所示，藉由等向性蝕刻遮 形成圖案寬度較遮罩材圖案1 4 a還要微、細έ 1 4 b。亦即，藉由等向性蝕刻以使遮罩材圖 (s h r i n k )或後退。該等向性蝕刻如係由1 C C 〇 u ρ 1 e d P 1 a s m a )餘刻裝置來進行’ #玄蚀刻 高頻功率：1 5 0 0 W (上部）/ 8 0 W (下部）High-frequency power: 15 0 W (upper) / 2 0 0 W (lower) Pressure: 30 mT Gas: 〇2 / Cl2 = 100 / 10sccm Next, as shown in Fig. 1 (c), The width of the pattern of the masking pattern is slightly smaller and thinner than that of the masking material pattern 1 4 a. That is, the mask material pattern (shrnik) is retracted by isotropic etching. The isotropic etching is performed by a 1 C C 〇 u ρ 1 e d P 1 a s m a) device. ’# 玄 刻 High-frequency power: 15 0 0 W (upper) / 8 0 W (lower)

壓力：2 OmT 氣體：〇2/Cl2=160/20sccm 然後，如圖1 ( d )所示，除去抗#劑圖案 接著，如圖1 ( e )所示，藉由將遮罩材圖； 而異向性蝕刻閘極佈線材料1 3 ^ ^ 向性蝕刻如係由ECR蝕刻裝置來進行’該^ 下。 高頻功率：4 0 0 W (上部）/ 3 0 W (下部） 壓力：4mTorr 312/發明說明書(補件)/92-11 /92124080 罩材1 4上形成 案1 5作為遮罩 1 4 a。該異向性 a s m a )蚀刻裝置 罩材圖案1 4 a， ί勺遮罩材圖案 案1 4 a收縮 P( Inductively 條件成為如下。 15° 奪1 4 b作為遮罩 佈線1 3 a。該異 丨虫刻條件成為如 7 200409197 氣體：HBr/Cl2/〇2=70/30/50sccm 最後，如圖1(f)所示，藉由除去遮罩材圖案14b，於閘 極絕緣膜1 2上形成閘極佈線1 3 a。該遮罩材圖案1 4 b的除 去如係由降流灰化型拋光裝置來進行，該拋光條件成為如 下。Pressure: 2 OmT Gas: 〇2 / Cl2 = 160 / 20sccm Then, as shown in FIG. 1 (d), the anti- # agent pattern is removed. Then, as shown in FIG. 1 (e), the mask material is drawn; and The anisotropic etching of the gate wiring material 1 3 ^ ^ Anisotropic etching is performed by an ECR etching apparatus. High-frequency power: 4 0 0 W (upper) / 3 0 W (lower) Pressure: 4mTorr 312 / Invention Manual (Supplement) / 92-11 / 92124080 Case 1 on the cover material 1 4 as the cover 1 4 a . The anisotropic etching device cover material pattern 1 4 a, the spoon mask material pattern 1 4 a shrinks P (Inductively conditions become as follows. 15 ° 1 14 b as the mask wiring 1 3 a. The insect-engraving conditions are as follows: 200409197 Gas: HBr / Cl2 / 〇2 = 70/30 / 50sccm Finally, as shown in FIG. 1 (f), the mask material pattern 14b is removed and formed on the gate insulating film 12 Gate wiring 1 3 a. The removal of the mask material pattern 1 4 b is performed by a downflow ashing type polishing device, and the polishing conditions are as follows.

微波電力：1 4 0 0 W 壓力：2 T 〇 r rMicrowave power: 1 4 0 0 W Pressure: 2 T 〇 r r

氣體：〇2/N2=900/100sccm 溫度：2 0 0 °C 如上述說明，本實施形態中，係將金屬膜之釕膜形成作 為遮罩材。藉由將抗蝕劑圖案1 5作為遮罩的異向性蝕刻而 形成遮罩材圖案1 4 a後，藉由實施等向性蝕刻以使遮罩材 圖案1 4 a收縮，藉由將該已收縮的遮罩材圖案1 4 b作為遮 罩的異向性#刻而形成閘極佈線1 3 a。 根據本實施形態1，作為閘極佈線材料1 3的多晶矽膜， 相對於作為遮罩材1 4的釕膜具有高蝕刻選擇比，因此，可 防止遮罩材的削肩等的圖案劣化。又，作為遮罩材1 4的釕 膜的除去，對於閘極佈線材料（多晶矽膜）或閘極絕緣膜（氧 化膜）具有高選擇比。因此可容易選擇除去遮罩材圖案14b 而不致削去閘極佈線1 3 a。藉此，可防止閘極佈線1 3 a的 膜厚變化。據此，可容易形成所需的形狀的閘極佈線1 3 a。 另外，因為可容易進行遮罩材的收縮，容易獲得微細的 遮罩材圖案14b，因此將此遮罩材圖案作為遮罩可容易形 成微細圖案（微細閘極佈線1 3 a )。 8 312/發明說明書(補件)/92-11/92124080 200409197 又，本實施形態1中，雖作為遮罩材14而使用釕月 但並不限於此，也可使用如鎢（W )膜或氮化鈦（T i N )膜 屬膜。在此，在將鐵（W )膜用作為遮罩材1 4的情況， 將Η 2 0 2水溶液用於遮罩材的收縮或除去，可獲得與將 用作為遮罩的情況相同的效果。另外，在將氮化鈦膜 為遮罩材1 4的情況，藉由將Η 2 0 2水溶液用於遮罩材ί 縮或除去，可獲得與此等相同的效果。 另外，本實施形態1中，係在使遮罩材圖案收縮後 去抗蝕劑圖案1 5，但是，也可將順序相反。也就是說 藉由將抗蝕劑圖案1 5作為遮罩的蝕刻以形成遮罩材S 案，而除去抗蝕劑圖案1 5後，也可使遮罩材圖案收縮 情況，因為在收縮時遮罩材圖案上面也被收縮，因此 罩14的形成膜厚形成為如60nm的厚度。 (實施形態2 ) 圖2為說明本發明之實施形態2之半導體裝置之製 法用的剖面圖。詳細而言，圖2與圖1相同，為說明 等之微細的閘極佈線的形成方法用的圖。 首先，如圖2 ( a)所示，利用與前述實施形態1相同 法（參照圖1 ( a ))，在矽晶圓1 1上，形成閘極絕緣膜 閘極佈線材料1 3、作為遮罩材1 4的釕（R u )膜及抗蝕 案15。 接著，如圖2 ( b )所示，利用與實施形態1相同的方：¾ 照圖1 ( b ))，形成遮罩材圖案1 4 a。 接著，如圖2 ( c )所示，藉由等向性蝕刻抗蝕劑圖案 312/發明說明書(補件)/92-11 /92124080 的金 藉由 釕膜 用作 勺收 以除 ，在 0該 將遮 造方 ASIC 的方 12、 劑圖 (參 15 9 200409197 及遮罩材圖案1 4 a。藉此，將抗蝕劑圖案1 5及遮罩材圖案 1 4 a收縮或後退。該等向性I虫刻如係由I C P ( I n d u c t i v e 1 y C o u p 1 e d P 1 a s m a )姓刻裝置來進行，該钱刻條件成為如下。 高頻功率：1 5 0 0 W (上部）/ 5 0 W (下部）Gas: 〇2 / N2 = 900 / 100sccm Temperature: 2000 ° C As described above, in this embodiment, a ruthenium film of a metal film is formed as a masking material. After the mask material pattern 1 4 a is formed by anisotropic etching using the resist pattern 15 as a mask, the isotropic etching is performed to shrink the mask material pattern 1 4 a. The contracted masking material pattern 1 4 b is engraved as an anisotropic mask of the mask to form a gate wiring 1 3 a. According to the first embodiment, the polycrystalline silicon film serving as the gate wiring material 13 has a higher etching selectivity than the ruthenium film serving as the masking material 14, so that pattern degradation such as shaving of the masking material can be prevented. In addition, the removal of the ruthenium film as the masking material 14 has a high selection ratio for a gate wiring material (polycrystalline silicon film) or a gate insulating film (oxide film). Therefore, the mask material pattern 14b can be easily removed without cutting off the gate wiring 1 3a. This can prevent a change in the film thickness of the gate wiring 13a. This makes it possible to easily form the gate wiring 1 3 a having a desired shape. In addition, since the shrinkage of the masking material can be easily performed and a fine masking material pattern 14b can be easily obtained, a fine pattern can be easily formed using this masking material pattern as a mask (fine gate wiring 1 3 a). 8 312 / Invention Specification (Supplement) / 92-11 / 92124080 200409197 In the first embodiment, although ruthenium is used as the cover material 14, it is not limited to this. For example, a tungsten (W) film or A titanium nitride (TiN) film is a film. Here, when an iron (W) film is used as the masking material 14 and an aqueous solution of Η202 is used for the shrinkage or removal of the masking material, the same effects as those obtained when the masking material is used can be obtained. In the case where a titanium nitride film is used as the masking material 14, the same effect can be obtained by using a Η2 02 aqueous solution for shrinking or removing the masking material. In the first embodiment, the resist pattern 15 is removed after the masking material pattern is shrunk. However, the order may be reversed. That is to say, the mask pattern S is formed by etching with the resist pattern 15 as a mask, and the mask pattern can be shrunk after the resist pattern 15 is removed, because Since the upper surface of the cover material pattern is also shrunk, the formation film thickness of the cover 14 is formed to a thickness of, for example, 60 nm. (Embodiment 2) FIG. 2 is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention. Specifically, FIG. 2 is the same as FIG. 1 and is a diagram for explaining a method for forming a fine gate wiring. First, as shown in FIG. 2 (a), a gate insulating film and a gate wiring material 1 3 are formed on a silicon wafer 11 using the same method as in the first embodiment (see FIG. 1 (a)). Ruthenium (R u) film and resist 15 for cover material 14. Next, as shown in FIG. 2 (b), the same method as in Embodiment 1 is used: ¾ According to FIG. 1 (b)), a mask material pattern 1 4a is formed. Next, as shown in FIG. 2 (c), the gold of the resist pattern 312 / Invention Specification (Supplement) / 92-11 / 92124080 by isotropic etching is used to collect and divide the gold by using a ruthenium film at 0. This will cover the recipe of the ASIC, the agent map (refer to 15 9 200409197 and the mask material pattern 1 4 a. In this way, the resist pattern 15 and the mask material pattern 1 4 a will shrink or retreat. These Orientation I insect carving is performed by the ICP (Inductive 1 y Coup 1 ed P 1 asma) surname engraving device, the conditions for the money carving are as follows. High-frequency power: 1 5 0 0 W (upper) / 5 0 W (lower)

壓力：5 OmT 氣體：0 2 / C 1 2 = 2 0 0 / 2 0 s c c m 然後，如圖2 ( d )所示，將已收縮的抗蝕劑圖案1 5 a及遮 罩材圖案1 4 b作為遮罩而藉由異向性蝕刻除去閘極佈線材 料1 3，形成閘極佈線1 3 a。該異向性I虫刻如係由E C R I虫刻 裝置來進行，該蝕刻條件成為如下。 高頻功率：4 0 0 W (上部）/ 3 0 W (下部） 壓力：4mTorr 氣體：HBr/Cl2/〇2=70/30/50sccm 最後，如圖2(e)所示，藉由除去遮罩材圖案15a與遮罩 材圖案1 4 b，於閘極絕緣膜1 2上形成閘極佈線1 3 a。該遮 罩材圖案1 5 a與遮罩材圖案1 4 b的除去如係由降流灰化型 拋光裝置來進行，該拋光條件成為如下。Pressure: 5 OmT Gas: 0 2 / C 1 2 = 2 0 0/2 0 sccm Then, as shown in FIG. 2 (d), shrink the resist pattern 1 5 a and the mask material pattern 1 4 b The gate wiring material 1 3 is removed as a mask by anisotropic etching to form a gate wiring 1 3 a. The anisotropic I insect engraving is performed by an E C R I insect engraving device, and the etching conditions are as follows. High frequency power: 4 0 0 W (upper) / 3 0 W (lower) Pressure: 4mTorr Gas: HBr / Cl2 / 〇2 = 70/30 / 50sccm Finally, as shown in Figure 2 (e), The cover material pattern 15 a and the cover material pattern 1 4 b form a gate wiring 1 3 a on the gate insulating film 12. The removal of the masking material pattern 15 a and the masking material pattern 1 4 b is performed by a downflow ashing type polishing apparatus, and the polishing conditions are as follows.

微波功率：1 4 0 0 W 壓力：2 T 〇 r r 氣體：Ο 2 / N 2 = 9 Ο Ο / 1 Ο 0 s c c mMicrowave power: 1 4 0 0 W Pressure: 2 T 〇 r r Gas: 〇 2 / N 2 = 9 〇 〇 / 1 〇 0 s c c m

溫度：2 Ο 0 °C 如上述說明，本實施形態2中，藉由將抗蝕劑圖案1 5 作為遮罩的異向性蝕刻而形成遮罩材圖案1 4 a後，藉由實 施等向性蝕刻以使抗蝕劑圖案1 5與遮罩材圖案1 4 a收縮， 10 312/發明說明書(補件)/92-11/92124080 200409197 藉由將該已收縮的遮罩材圖案1 5 a及遮罩材圖案1 4 b作為 遮罩的異向性蝕刻而形成閘極佈線1 3 a。其後，同時除去 遮罩材圖案15a及遮罩材圖案14b。 根據本實施形態2，在閘極佈線1 3 a形成後，利用除去 屬遮罩材圖案1 4 b的釕膜的條件，可同時除去遮罩材圖案 1 4 b與抗蝕劑圖案1 5。 藉此，除可獲得實施形態1的效果外，還可獲得不需要 在將圖案改寫於釕膜上後僅除去抗蝕劑圖案1 5的步驟，而 可減少製造步驟數的效果。 (實施形態3 ) 圖3為說明本發明之實施形態3之半導體裝置之製造方 法用的剖面圖。詳細而言，圖3為說明A S I C或D R A Μ等之 記憶元件上之連接於金屬佈線之通孔的形成方法用的剖面 圖。 首先，如圖3 ( a )所示，在基板（省略圖示）上形成下層佈 線2 1，在下層佈線2 1上形成1 . 5 // m膜厚的用作為層間絕 緣膜2 2的氧化矽膜（例如，T E 0 S膜、B S G膜、B P S G膜等）。 接著，在層間絕緣膜2 2上形成3 0 n m膜厚的用作為遮罩材 2 4的釕膜。然後於遮罩材2 4上形成抗餘劑圖案2 5。 接著，如圖3 ( b )所示，藉由將抗蝕劑圖案2 5作為遮罩 而異向性蝕刻遮罩材2 4，形成遮罩材圖案2 4 a。該異向性 I虫刻如係由 I C P ( I n d u c t i v e 1 y C 〇 u p 1 e d P 1 a s m a ) I虫刻裝置 來進行，該餘刻條件成為如下。 高頻功率：1 5 0 0 W (上部）/ 2 0 0 W (下部） 11 312/發明說明書(補件)/92-11 /92124080 200409197 壓力：3 0 m Τ 氣體：〇2/Cl2=100/10sccm 接著，如圖3 ( c )所示，藉由異向性14刻抗#劑圖案2 5 與遮罩材圖案2 4 a，形成從層間絕緣膜2 2的表面到達下層 佈線2 1的通孔2 6。該異向性蝕刻如係由E C R蝕刻裝置來 進行，該#刻條件成為如下。 高頻功率：1 7 0 0 W (上部）/ 7 0 0 W (下部） 壓力：4mTorr 氣體：C4F8/Ar/CO=25/200/20sccm 最後，如圖3 ( d )所示，藉由除去抗蝕劑圖案2 5與遮罩 材圖案2 4 a，於層間絕緣膜2 2内形成聯繫下層佈線21的 通孔2 6。該抗蝕劑圖案2 5與遮罩材圖案2 4 a的除去如係 由降流灰化型拋光裝置來進行，該拋光條件成為如下。Temperature: 2 0 0 ° C As described above, in the second embodiment, a masking material pattern 1 4 a is formed by anisotropic etching using the resist pattern 15 as a mask, and then isotropic orientation is performed. Etching to shrink the resist pattern 15 and the mask material pattern 1 4 a, 10 312 / Invention Specification (Supplement) / 92-11 / 92124080 200409197 by shrinking the mask material pattern 1 5 a And the mask material pattern 1 4 b is anisotropically etched as a mask to form the gate wiring 1 3 a. Thereafter, the masking material pattern 15a and the masking material pattern 14b are simultaneously removed. According to the second embodiment, after the gate wiring 13a is formed, the masking material pattern 14b and the resist pattern 15 can be removed at the same time under the condition that the ruthenium film belonging to the masking material pattern 14b is removed. Thereby, in addition to the effect of the first embodiment, an effect of reducing the number of manufacturing steps without the step of removing only the resist pattern 15 after rewriting the pattern on the ruthenium film can be obtained. (Embodiment 3) Fig. 3 is a sectional view for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention. In detail, FIG. 3 is a cross-sectional view for explaining a method of forming a through-hole connected to a metal wiring on a memory element such as A S IC or D R AM. First, as shown in FIG. 3 (a), a lower-layer wiring 21 is formed on a substrate (not shown), and an oxidation of an interlayer insulating film 2 2 with a film thickness of 1.5 m is formed on the lower-layer wiring 21. Silicon film (for example, TE 0 S film, BSG film, BPSG film, etc.). Next, a ruthenium film serving as a masking material 24 was formed on the interlayer insulating film 22 to a thickness of 30 nm. Then, an anti-residue pattern 25 is formed on the masking material 24. Next, as shown in FIG. 3 (b), the mask material 24 is anisotropically etched by using the resist pattern 25 as a mask to form a mask material pattern 2a. The anisotropic I engraving is performed by an I C P (I n d u c t i v e 1 y C o p 1 e d P 1 a s m a) I engraving device, and the remaining conditions are as follows. High-frequency power: 15 0 0 W (upper) / 2 0 0 W (lower) 11 312 / Invention Manual (Supplement) / 92-11 / 92124080 200409197 Pressure: 3 0 m Τ Gas: 〇2 / Cl2 = 100 / 10sccm Next, as shown in FIG. 3 (c), an anisotropic 14-carving anti- # agent pattern 2 5 and a masking material pattern 2 4 a are formed to form a layer from the surface of the interlayer insulating film 2 2 to the lower-layer wiring 2 1. Through holes 2 6. The anisotropic etching is performed by an E C R etching apparatus, and the #etching conditions are as follows. High-frequency power: 1 7 0 0 W (upper) / 7 0 0 W (lower) Pressure: 4mTorr Gas: C4F8 / Ar / CO = 25/200 / 20sccm Finally, as shown in Figure 3 (d), by removing The resist pattern 25 and the mask material pattern 2 4 a form a through-hole 26 in the interlayer insulating film 22 to connect the lower-layer wiring 21. The removal of the resist pattern 25 and the mask material pattern 2 4 a is performed by a downflow ashing type polishing apparatus, and the polishing conditions are as follows.

微波功率：1 4 0 0 W 壓力：2 Τ 〇 r r 氣體：〇2/N2=900/100sccmMicrowave power: 1 4 0 0 W Pressure: 2 Τ 〇 r r Gas: 〇2 / N2 = 900 / 100sccm

溫度：2 0 0 °C 如上述說明，本實施形態3中，藉由將抗蝕劑圖案2 5 作為遮罩的異向性蝕刻而形成遮罩材圖案2 4 a後，藉由實 施將抗蝕劑圖案2 5與遮罩材圖案2 4 a作為遮罩的異向性蝕 刻，而於層間絕緣膜2 2内形成聯繫下層佈線2 1的通孔 26。其後，除去遮罩材圖案24a。 根據本實施形態3，作為遮罩材1 4的釕膜的除去，對於 層間絕緣膜、金屬材料及基板材料具有高選擇比。因此可 12 312/發明說明書(補件)/92-11 /92124080 200409197 容易選擇除去遮罩材圖案2 4 a，而不致削去層間絕緣膜 2 2、下層佈線2 1及基板。尤其是，藉由拋光乾式除去釕膜， 即使在類似佈線的金屬材料曝露於基板表面，仍無類似濕 式餘刻時的造成金屬材料的炫化的情況。藉此，可容易形 成所需形狀的通孔2 6，而不致削去層間絕緣膜及下層佈 線，亦即無圖案的劣化。 另外，本實施形態3中，在通孔2 6形成後，利用除去 遮罩材圖案2 4 a的條件，可同時除去遮罩材圖案2 4 a與抗 蝕劑圖案2 5。藉此，可獲得不需要在將圖案改寫於釕膜上 後僅除去抗蝕劑圖案2 5的步驟，而可減少製造步驟數的效 果。 又，本實施形態3中，說明了聯繫於下層佈線21的通 孔的形成方法，但是，本發明也同樣適用於聯繫於基板的 通孔的形成。該情況，因為可將濕式蝕刻用於光罩材的除 去，因此可由釕膜以外的金屬膜之鎢膜及氮化鈦膜來形成 作為光罩材。鐵膜的除去可使用H2O2水溶液，而氮化鈦膜 的除去可使用H2SO4水溶液。 另外，雖然製造步驟數有增加，如實施形態1般，也可 在形成遮罩材圖案2 4 a後，僅除去抗蝕劑圖案2 5，而將遮 罩材圖案2 4 a作為遮罩形成通孔2 6。 (發明效果） 根據本發明，可選擇性除去遮罩材而不致削去被加工 膜。另夕卜，根據本發明，可容易形成微細圖案。 【圖式簡單說明】 13 312/發明說明書(補件)/92-11 /92124080 200409197 圖1 ( a )〜（f )為說明本發明之實施形態1之半導體裝置 之製造方法用的剖面圖。 圖2 ( a )〜（e )為說明本發明之實施形態2之半導體裝置 之製造方法用的剖面圖。 圖3 ( a )〜（d )為說明本發明之實施形態3之半導體裝置 之製造方法用的剖面圖。 圖4為說明以往之半導體裝置之製造方法的問題用的剖 面圖。 (元件符號說明） 11 基板（矽晶圓） 12 閘極絕緣膜（閘極氧化膜） 13 閘極佈線材料（多晶矽膜） 13a 閘極佈線 14 遮罩材（釕膜） 14a 遮罩材圖案 14b 遮罩材圖案 15 抗蝕劑圖案 2 1 下層佈線 22 層間絕緣膜（氧化矽膜） 24 遮罩材（釕膜） 24a 遮罩材圖案 25 抗蝕劑圖案 2 6 通孔 14 312/發明說明書(補件)/92-11 /92124080Temperature: 2 0 0 ° C As described above, in the third embodiment, the mask material pattern 2 4 a is formed by anisotropic etching using the resist pattern 2 5 as a mask, and then the resist The resist pattern 25 and the mask material pattern 2 4 a serve as anisotropic etching for the mask, and a through hole 26 is formed in the interlayer insulating film 22 to connect the lower-layer wiring 21. Thereafter, the mask material pattern 24a is removed. According to the third embodiment, the removal of the ruthenium film as the masking material 14 has a high selection ratio for the interlayer insulating film, the metal material, and the substrate material. Therefore, 12 312 / Invention Specification (Supplement) / 92-11 / 92124080 200409197 can easily choose to remove the masking material pattern 2 4 a without cutting off the interlayer insulating film 2 2, the lower wiring 21 and the substrate. In particular, by removing the ruthenium film dry by polishing, even when a metal material like a wiring is exposed on the surface of the substrate, there is still no glare of the metal material like in the wet type. Thereby, the through-holes 26 of a desired shape can be easily formed without cutting off the interlayer insulating film and the underlying wiring, that is, without pattern deterioration. In addition, in the third embodiment, after the through-holes 26 are formed, the masking material pattern 2 4 a and the resist pattern 25 can be simultaneously removed under the condition that the masking material pattern 2 4 a is removed. This makes it possible to obtain an effect that it is not necessary to remove the resist pattern 25 only after the pattern is rewritten on the ruthenium film, and the number of manufacturing steps can be reduced. In the third embodiment, a method of forming a via hole related to the lower-layer wiring 21 has been described. However, the present invention is also applicable to the formation of a via hole related to a substrate. In this case, since wet etching can be used for the removal of the mask material, a tungsten film and a titanium nitride film of a metal film other than a ruthenium film can be used as the mask material. The H2O2 aqueous solution can be used for the removal of the iron film, and the H2SO4 aqueous solution can be used for the removal of the titanium nitride film. In addition, although the number of manufacturing steps has increased, as in Embodiment 1, after forming the mask material pattern 2 4 a, only the resist pattern 25 can be removed and the mask material pattern 2 4 a can be formed as a mask. Through holes 2 6. (Effects of the Invention) According to the present invention, the masking material can be selectively removed without removing the processed film. In addition, according to the present invention, a fine pattern can be easily formed. [Brief Description of the Drawings] 13 312 / Invention Specification (Supplement) / 92-11 / 92124080 200409197 Figures 1 (a) to (f) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. 2 (a) to (e) are cross-sectional views for explaining a method for manufacturing a semiconductor device according to a second embodiment of the present invention. 3 (a) to (d) are cross-sectional views for explaining a method of manufacturing a semiconductor device according to a third embodiment of the present invention. Fig. 4 is a cross-sectional view for explaining a problem in a conventional method of manufacturing a semiconductor device. (Description of component symbols) 11 Substrate (silicon wafer) 12 Gate insulating film (gate oxide film) 13 Gate wiring material (polycrystalline silicon film) 13a Gate wiring 14 Masking material (ruthenium film) 14a Masking material pattern 14b Mask material pattern 15 Resist pattern 2 1 Lower wiring 22 Interlayer insulating film (silicon oxide film) 24 Mask material (ruthenium film) 24a Mask material pattern 25 Resist pattern 2 6 Through hole 14 312 / Invention specification ( Supplement) / 92-11 / 92124080

Claims (1)

200409197 拾、申請專利範圍： 1. 一種半導體裝置之製造方法，其特徵為具備如下步 驟： 於基板上形成被加工膜的步驟； 於上述被加工膜上形成遮罩材的步驟； 於上述遮罩材上形成抗蝕劑圖案的步驟； 將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩材的 步驟； 使上述圖案處理過的上述遮罩材收縮的步驟； 將已收縮的上述遮罩材作為遮罩而圖案加工上述被加 工膜的步驟；及 除去上述遮罩材的步驟。 2. 如申請專利範圍第1項之半導體裝置之製造方法，其 中，以金屬膜來形成上述遮罩材。 3 .如申請專利範圍第2項之半導體裝置之製造方法，其 中： 以釕膜來形成上述遮罩材； 使用含氧的電漿來除去上述遮罩材，同時除去上述抗蝕 劑圖案。 4. 一種半導體裝置之製造方法，其特徵為具備如下步 驟： 於基板上形成被加工膜的步驟； 於上述被加工膜上形成作為遮罩材的釕膜的步驟； 於上述遮罩材上形成抗蝕劑圖案的步驟； 15 312/發明說明書(補件)/92-11/92124080 200409197 將上述抗蝕劑圖案作為遮罩而圖案加工上述遮罩材的 步驟； 將已圖案處理的上述遮罩材作為遮罩而圖案加工上述 被加工膜的步驟；及 除去上述遮罩材的步驟。 5 .如申請專利範圍第4項之半導體裝置之製造方法，其 中，使用含氧的電漿來除去上述遮罩材，同時除去上述抗 I虫劑圖案。 6 .如申請專利範圍第5項之半導體裝置之製造方法，其 中，在金屬材料曝露於上述基板上的狀態，除去上述遮罩 材。 16 312/發明說明書(補件)/92-11 /92124080200409197 Patent application scope: 1. A method for manufacturing a semiconductor device, which is characterized by having the following steps: a step of forming a processed film on a substrate; a step of forming a masking material on the processed film; and the above mask A step of forming a resist pattern on the material; a step of patterning the mask material using the resist pattern as a mask; a step of shrinking the mask material treated by the pattern; a shrinking mask A step of patterning the film to be processed with the material as a mask; and a step of removing the mask material. 2. The method for manufacturing a semiconductor device according to item 1 of the patent application scope, wherein the mask material is formed by a metal film. 3. The method for manufacturing a semiconductor device according to item 2 of the scope of patent application, wherein: the masking material is formed with a ruthenium film; the masking material is removed using an oxygen-containing plasma, and the resist pattern is removed at the same time. 4. A method for manufacturing a semiconductor device, comprising the steps of: forming a processed film on a substrate; forming a ruthenium film as a masking material on the processed film; and forming on the masking material Step of resist pattern; 15 312 / Invention specification (Supplement) / 92-11 / 92124080 200409197 Step of patterning the masking material by using the resist pattern as a mask; patterning the mask A step of patterning the film to be processed with the material as a mask; and a step of removing the mask material. 5. The method for manufacturing a semiconductor device according to item 4 of the scope of patent application, wherein the masking material is removed using an oxygen-containing plasma, and the anti-I insecticide pattern is removed at the same time. 6. The method of manufacturing a semiconductor device according to item 5 of the patent application, wherein the masking material is removed in a state where a metal material is exposed on the substrate. 16 312 / Invention Specification (Supplement) / 92-11 / 92124080
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