TWI220768B

TWI220768B - Method of forming a gate and method of forming a contact window

Info

Publication number: TWI220768B
Application number: TW92124426A
Authority: TW
Inventors: Fang-Yu Yeh; Chi Lin; Chia-Yao Chen
Original assignee: Promos Technologies Inc
Priority date: 2003-09-04
Filing date: 2003-09-04
Publication date: 2004-09-01
Also published as: TW200511399A

Abstract

A method of forming a gate is described. A substrate including a memory cell area and a periphery area is provided, wherein a dielectric layer, a first conductive layer, and a second conductive layer have been formed on the substrate. A mask layer is formed on the second conductive layer. A first etching process is preformed to remove the second conductive layer by using the mask layer to be an etching mask, until the surface of the first conductive layer in the memory cell area or the periphery area is exposed. A second etching process is performed to remove a partial thickness of the sidewalls of the second conductive layer, and the etching selectivity of the second conductive layer is bigger than that of the first conductive layer for the second etching process. A first thermal process is performed. A third etching process is preformed to remove the first conductive layer by using the mask layer to be an etching mask, until the surface of the dielectric layer in the memory cell array area and the periphery area is exposed.

Description

1220768 五、發明說明（1) 【發明所屬之技術領域】本發明是有關於一種半導體製程，且特別是有關於一種閘極的製造方法以及接觸窗開口的製造方法。【先前技術】在現今之金氧半導體元件中，多晶矽化金屬閘極係為普遍採用的一種閘極結構，一般而言，多晶石夕化金屬閘極的結構通常是在閘極的多晶矽層上形成耐熱金屬矽化物 (Refractory Metal Silicide)層，例如是石夕化鐵等，並藉由耐熱金屬矽化物所具有之熔點高、穩定性高、及電阻率（R e s i s t i v i t y )低等優點，從而提昇金屬與石夕之間的歐姆式接觸性（0 h m i c C ο n t a c t )，以及增加金氧半導體之閘極結構的導電特性。第1 A圖至第1 E圖，其繪示是習知一種多晶矽化金屬閘極的製造流程剖面示意圖。請參照第1 A圖，提供具有記憶胞陣列區1 0 2與周邊電路區103之基底100 ，且基底100上已形成有介電層104、多晶矽層1 0 6、矽化金屬層1 0 8以及圖案化之罩幕層1 1 0。接著，請參照第1 B圖，進行蝕刻製程，以移除記憶胞陣列區1 0 2與周邊電路區1 0 3之多晶矽層1 0 6與矽化金屬層 1 0 8直至裸露出介電層1 0 4為止，並且同時於記憶胞陣列區 102與周邊電路區103分別定義出由介電層104 、多晶矽層 1 0 6 a與矽化金屬層1 0 8 a所構成的閘極1 1 2 a、1 1 2 b。然而，由於記憶胞陣列區1 0 2所欲定義之閘極1 1 2 a的分布密度會大於周邊電路區103中所欲定義之閘極112b的1220768 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor process, and in particular, to a method for manufacturing a gate electrode and a method for manufacturing a contact window opening. [Previous technology] In today's metal-oxide-semiconductor devices, polysilicon metal gates are a commonly used gate structure. Generally speaking, the structure of polycrystalline silicon gates is usually a polycrystalline silicon layer on the gate. A refractory metal silicide (Refractory Metal Silicide) layer is formed thereon, and the refractory metal silicide has the advantages of high melting point, high stability, and low resistivity. Improve the ohmic contact between metal and Shi Xi (0 hmic C ο ntact), and increase the conductive properties of the gate structure of the metal-oxide semiconductor. FIG. 1A to FIG. 1E are cross-sectional schematic diagrams showing the manufacturing process of a conventional polysilicon metal gate. Referring to FIG. 1A, a substrate 100 having a memory cell array region 102 and a peripheral circuit region 103 is provided. A dielectric layer 104, a polycrystalline silicon layer 106, a silicided metal layer 108, and a substrate 100 have been formed on the substrate 100. Patterned mask layer 1 1 0. Next, referring to FIG. 1B, an etching process is performed to remove the polycrystalline silicon layer 1 0 6 and the silicide metal layer 1 0 8 of the memory cell array region 102 and the peripheral circuit region 103 until the dielectric layer 1 is exposed. Up to 0, and at the same time in the memory cell array area 102 and the peripheral circuit area 103, a gate electrode 1 1 2 a composed of a dielectric layer 104, a polycrystalline silicon layer 10 6 a and a silicided metal layer 1 0 8 a, 1 1 2 b. However, the distribution density of the gates 1 1 2 a to be defined in the memory cell array region 102 is larger than that of the gates 112 b to be defined in the peripheral circuit region 103.

11639twf.ptd 第8頁 1220768 五、發明說明（2) 分布费度，如此會造成不同區域其蚀刻速度不同，此稱為負載效應（1 〇 a d i n g e f f e c t )，亦即在蝕刻過程中，當周邊電路區1 〇 3已裸露出介電層1 0 4時，在記憶胞陣列區1 〇 2中仍有未餘刻的多晶石夕層1 0 6 b。接著，請參照第1 C圖，繼續進行餘刻製程，以將記憶胞陣列區1 〇 2中未蝕刻完全的多晶矽層1 0 6 b去除。然而，由於介電層1 0 4與多晶矽層（1 0 6 a與1 0 6 b )之蝕刻選擇比並不高，所以在去除記憶胞陣列區1 0 2之殘存的多晶矽層 106b時，還會使得周邊電路區1〇3之部分介電層1〇4被移除。接著，請參照第1 D圖，進行矽化金屬層1 〇 8 a之蝕刻步驟，以移除矽化金屬層1 0 8 a側壁之部分厚度，使得矽化金屬層108b較其他膜層凹陷。之後，請參照第1 E圖，進行快速熱回火製程（R ap i d Thermal Annealing ，RTA)/ 快速熱氧化（Rapid Thermal Oxidation，RTO)製程，以穩定矽化金屬層l〇8b，並且同時在閘極（1 1 2 a與1 1 2 b )之側壁以及未被閘極（1 1 2 a與1 1 2 b ) 覆蓋之基底100表面上形成一襯氧化層（oxide liner)114。由於在先前步驟中已先移除矽化金屬層i〇8a 側壁之部分厚度，因此在上述之熱製程中，可以避免矽化金屬層108c因晶粒成長而造成側面凸起（lateral extrusion) ° 然而，在上述之製程中具有下述的問題：雖然利用上述之快速熱回火製程可以使得矽化金屬層11639twf.ptd Page 8 1220768 V. Description of the invention (2) Distribution cost, which will cause different areas to have different etching speeds. This is called the load effect (10adingeffect), that is, during the etching process, when the peripheral circuit area When the dielectric layer 104 has been exposed at 103, there is still an unremained polycrystalline layer 106b in the memory cell array region 102. Next, referring to FIG. 1C, the remaining etching process is continued to remove the incompletely etched polycrystalline silicon layer 10 6 b in the memory cell array region 102. However, since the etching selection ratio of the dielectric layer 104 and the polycrystalline silicon layer (106a and 106b) is not high, when the remaining polycrystalline silicon layer 106b in the memory cell array region 102 is removed, A part of the dielectric layer 104 in the peripheral circuit area 103 will be removed. Next, referring to FIG. 1D, an etching step of the silicided metal layer 108a is performed to remove a part of the thickness of the sidewall of the silicided metal layer 108a, so that the silicided metal layer 108b is recessed compared to other film layers. After that, please refer to FIG. 1E to perform a rapid thermal annealing (RTA) / rapid thermal oxidation (RTO) process to stabilize the silicided metal layer 108b, and simultaneously An oxide liner 114 is formed on the sidewalls of the electrodes (1 1 2 a and 1 1 2 b) and the surface of the substrate 100 not covered by the gates (1 1 2 a and 1 1 2 b). Since the thickness of the side wall of the silicided metal layer 108 has been removed in the previous step, during the above thermal process, lateral extrusion of the silicided metal layer 108c due to grain growth can be avoided. However, The above process has the following problems: Although the rapid thermal tempering process described above can be used to make the silicided metal layer

11639twf.ptd 第9頁 1220768 五、發明說明（3) 1 0 8 b之晶格重新排列，並藉此穩定（s t a b 1 i z e )矽化金屬層 108b的性質。但是，在另一方面，在熱製程中所產生之熱應力卻會造成多晶矽層1 0 6 a形變（如第2圖所示），而多晶矽層1 0 6 a形變傾斜後，往往會使得後續製程，例如是接觸窗製程發生插塞與閘極短路的情形。此外，關於記憶胞陣列區1 0 2與周邊電路區1 0 3的蝕刻速度不同的問題，雖然可以利用再次蝕刻，來去除記憶胞陣列區1 0 2未I虫刻完全的多晶石夕層1 0 6 b。但是，再次#刻的結果可能導致過度蝕刻介電層1 0 4，而造成基底1 0 0的表面被損傷，特別是在現今欲增加閘極之導電性，而使多晶矽層1 0 6 a越來越薄的情況下，基底1 0 0表面被損傷的問題會更為嚴重。因此，在必須同時考慮到不使記憶胞陣列區 1 0 2殘留多晶矽層1 0 6 a，並避免周邊電路區1 0 3被過度蝕刻而損害基底1 0 0的情況下，必須更精準掌握其蝕刻終點，從而使得製程裕度非常的小。【發明内容】因此，本發明的目的就是提供一種閘極的製造方法以及接觸窗開口的製造方法，以解決習知在定義閘極時，在基底之記憶胞陣列區與周邊電路區，因負載效應（1 〇 a d i n g effect)不同而造成蝕刻速率不同，進而導致部分區域之基底表面被過度蝕刻的問題。本發明的另一目的就是提供一種閘極的製造方法以及接觸窗開口的製造方法，能夠提高在定義閘極結構時的製程裕度。11639twf.ptd Page 9 1220768 V. Description of the invention (3) The lattice of 1 0 8 b is rearranged, thereby stabilizing (s t a b 1 i z e) the properties of the silicided metal layer 108 b. However, on the other hand, the thermal stress generated during the thermal process will cause a deformation of the polycrystalline silicon layer 1 0 6 a (as shown in FIG. 2), and the deformation of the polycrystalline silicon layer 1 6 a often causes subsequent deformation The manufacturing process is, for example, a case where a plug and a gate are short-circuited in a contact window manufacturing process. In addition, regarding the problem that the etching rate of the memory cell array region 102 is different from that of the peripheral circuit region 103, it is possible to use the re-etching to remove the polycrystalline stone layer that is completely etched in the memory cell array region 102. 1 0 6 b. However, the result of #etching again may lead to over-etching of the dielectric layer 104, which may cause the surface of the substrate 100 to be damaged, especially in order to increase the conductivity of the gate electrode and make the polycrystalline silicon layer 106a more In the case of thinner and thinner, the problem of substrate 100 surface damage will be more serious. Therefore, in the case where the polycrystalline silicon layer 10 6 a is not left in the memory cell array region 102 and the peripheral circuit region 103 is not over-etched to damage the substrate 100, it must be more accurately grasped. Etching the end point, so that the process margin is very small. [Summary of the Invention] Therefore, an object of the present invention is to provide a method for manufacturing a gate electrode and a method for manufacturing a contact window opening, in order to solve the conventional problem in defining a gate electrode in a memory cell array region and a peripheral circuit region of a substrate due to load. The different etching effects result in different etching rates, which in turn leads to the problem that the substrate surface in some areas is over-etched. Another object of the present invention is to provide a method for manufacturing a gate electrode and a method for manufacturing a contact window opening, which can improve a process margin when defining a gate structure.

11639twf.ptd 第10頁 1220768 五、發明說明（4) 本發明的再一目的是提供一種的閘極製造方法以及接觸窗開口的製造方法，以解決習知在利用熱製程來穩定晶格時，其所產生之熱應力導致閘極之多晶石夕層產生形變的問題。本發明提出一種閘極的製造方法，此方法係首先提供具有記憶胞陣列區與周邊電路區之基底，此基底上已依序形成有介電層、第一導電層以及第二導電層。之後，於第二導電層上形成圖案化之罩幕層。接著，以此罩幕層為蝕刻罩幕，進行第一蝕刻製程，以移除第二導體層，直到記憶胞陣列區或周邊電路區之第一導電層之表面裸露出來為止。然後，進行第二蝕刻製程，以移除第二導電層側壁之部分厚度，其中第二蝕刻製程對於第二導電層之蝕刻選擇比大於對第一導電層之蝕刻選擇比。繼之，進行第一熱製程。隨後，以罩幕層為蝕刻罩幕，進行第三蝕刻製程，以移除第一導體層，直到記憶胞陣列區與周邊電路區之介電層之表面裸露出來為止。本發明提出一種接觸窗開口的製造方法，此方法係首先提供具有記憶胞陣列區與周邊電路區之基底，此基底上已依序形成有介電層、第一導電層以及第二導電層。之後，於第二導電層上形成圖案化之罩幕層。接著，以此罩幕層為蝕刻罩幕，進行第一蝕刻製程，以移除第二導體層，直到記憶胞陣列區或周邊電路區之第一導電層之表面裸露出來為止。然後，進行第二蝕刻製程，以移除第二導電層側壁之部分厚度，其中第二蝕刻製程對於第二導電層11639twf.ptd Page 10 1220768 V. Description of the invention (4) Another object of the present invention is to provide a method for manufacturing a gate electrode and a method for manufacturing a contact window opening, so as to solve the conventional problem when using a thermal process to stabilize a crystal lattice, The thermal stress generated by it causes deformation of the polycrystalline stone layer of the gate. The invention provides a gate manufacturing method. This method firstly provides a substrate having a memory cell array region and a peripheral circuit region. A dielectric layer, a first conductive layer, and a second conductive layer have been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the second conductive layer. Then, using this mask layer as an etching mask, a first etching process is performed to remove the second conductor layer until the surface of the first conductive layer in the memory cell array area or the peripheral circuit area is exposed. Then, a second etching process is performed to remove a part of the thickness of the side wall of the second conductive layer. The etching selection ratio of the second etching process for the second conductive layer is greater than the etching selection ratio of the first conductive layer. Then, the first thermal process is performed. Subsequently, a third etching process is performed using the mask layer as an etching mask to remove the first conductor layer until the surfaces of the dielectric layers of the memory cell array region and the peripheral circuit region are exposed. The invention provides a method for manufacturing a contact window opening. This method firstly provides a substrate having a memory cell array region and a peripheral circuit region. A dielectric layer, a first conductive layer, and a second conductive layer have been sequentially formed on the substrate. Thereafter, a patterned mask layer is formed on the second conductive layer. Then, using this mask layer as an etching mask, a first etching process is performed to remove the second conductor layer until the surface of the first conductive layer in the memory cell array area or the peripheral circuit area is exposed. Then, a second etching process is performed to remove a part of the thickness of the second conductive layer sidewall, wherein the second etching process is performed on the second conductive layer.

11639twf.ptd 第11頁 1220768 五、發明說明（5) 之蝕刻選擇比大於對第——導電層之蝕刻選擇比。繼之，進行第一熱製程。隨後，以罩幕層為蝕刻罩幕進行第三蝕刻製程，以移除第一導電層，直到記憶胞陣列區與周邊電路區的介電層之表面裸露出來為止，而形成複數個閘極結構。之後，進行第二熱製程，以在這些閘極結構的側壁與裸露之介電層上形成襯層。繼之，於這些閘極結構之側壁形成間隙壁。接著，於基底上方形成絕緣層，以覆蓋這些閘極結構。隨後，圖案化絕緣層，以在相鄰之其中二閘極結構之間形成接觸窗開口。由於在本發明中，第一次的钱刻製程只餘刻至第一導電層表面，之後利用對於第二導電層與第一導電層具有高蝕刻選擇比的濕式蝕刻製程，而能夠在幾乎不對第一導電層進行蝕刻的情況下，將記憶胞陣列區中未蝕刻完全的第二導電層去除，並同時移除兩區之第二導電層側壁之部分厚度，因此兩區之第一導電層的厚度相近，從而能夠避免習知周邊電路區的第一導電層厚度較薄，而於蝕刻製程中損害到基底表面的問題。而且，利用本發明之方法，係能夠使得在移除預定移除部分之第二導電層後，所預定移除部分之第一導電層具有相近的厚度，因此後續製程所需移除的第一導電層厚度相近，且蝕刻終點亦容易偵測，從而能夠有效提高製程的裕度。另外，本發明在未圖案化第一導電層之前，就先進行熱製程，以使第二導電層之晶格可以重新排列，並藉此穩11639twf.ptd Page 11 1220768 V. Description of the invention (5) The etching selection ratio of (5) is greater than the etching selection ratio of the first conductive layer. Then, the first thermal process is performed. Subsequently, a third etching process is performed using the mask layer as an etching mask to remove the first conductive layer until the surfaces of the dielectric layers of the memory cell array region and the peripheral circuit region are exposed to form a plurality of gate structures. . Then, a second thermal process is performed to form a liner on the sidewalls of the gate structures and the exposed dielectric layer. Next, a spacer is formed on the side walls of these gate structures. Next, an insulating layer is formed over the substrate to cover the gate structures. Subsequently, the insulating layer is patterned to form a contact window opening between two adjacent gate structures. In the present invention, the first money engraving process is only etched to the surface of the first conductive layer, and then a wet etching process having a high etching selectivity for the second conductive layer and the first conductive layer is used, and the Without etching the first conductive layer, the second conductive layer that is not etched completely in the memory cell array region is removed, and a part of the thickness of the side wall of the second conductive layer in the two regions is removed at the same time. The thicknesses of the layers are similar, thereby avoiding the problem that the thickness of the first conductive layer in the peripheral circuit region is known to be thin, and the substrate surface is damaged during the etching process. Moreover, by using the method of the present invention, after the second conductive layer of the predetermined removal portion is removed, the first conductive layer of the predetermined removal portion has a similar thickness, so the first The thicknesses of the conductive layers are similar, and the end point of the etching is easy to detect, which can effectively improve the margin of the process. In addition, before the first conductive layer is patterned in the present invention, a thermal process is performed first, so that the lattice of the second conductive layer can be rearranged and thereby stabilized.

11639t.wf.ptd 第12頁 1220768 五、發明說明（6) 定其性質，由於此時第一導電層尚為一整層的結構，因此習知因熱製程所產生之應力不會對第一導電層產生影響，而能夠避免第一導電層因為對第二導電層進行熱製程所產生之形變的問題，進而能夠避免在後續的接觸窗製程中產生插塞與閘極短路的問題。此外，由於本發明在進行第二導電層的熱製程後還會進行第一導電層的蝕刻製程，所以，即使熱製程造成第二導電層的側壁突出，亦能夠藉由餘刻第一導電層的蝕刻製程將之去除，而能夠避免開口或間距縮小的問題，並同樣能夠避免在後續的接觸窗製程中產生插塞與閘極短路的問題。為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下：【實施方式】第3 A圖至第3 E圖所示，其繪示依照本發明一較佳實施例的一種閘極的製造流程剖面示意圖。請參照第3 A圖，本發明之閘極的製造方法係先提供具有記憶胞陣列區2 0 2與周邊電路區2 0 3之基底2 0 0，此基底 200上已依序形成有介電層204與導電層（206與208)。其中，介電層2 0 4的材質例如是氧化矽，導電層2 0 6的材質例如是多晶石夕，導電層2 0 8的材質例如是石夕化金屬，而此石夕化金屬例如是石夕化鐵。另外，介電層2 0 4的材質例如是氧化石夕時，其形成的方法例如是熱氧化法，而導電層（2 0 6與11639t.wf.ptd Page 12 1220768 V. Description of the invention (6) Determine its properties. Since the first conductive layer is still a whole layer structure at this time, it is known that the stress caused by the thermal process will not affect the first layer. The conductive layer has an effect, which can avoid the problem of deformation of the first conductive layer due to the thermal process of the second conductive layer, and can further avoid the problem of plug and gate short circuit in the subsequent contact window process. In addition, since the present invention also performs an etching process of the first conductive layer after the thermal process of the second conductive layer, even if the sidewall of the second conductive layer is protruded by the thermal process, the first conductive layer can be etched by the remaining time. It can be removed by the etching process, which can avoid the problem of shrinking the opening or the gap, and can also avoid the problem of plug and gate short circuit in the subsequent contact window process. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Embodiment Mode] Figures 3A to FIG. 3E is a schematic cross-sectional view illustrating a manufacturing process of a gate electrode according to a preferred embodiment of the present invention. Please refer to FIG. 3A. The manufacturing method of the gate of the present invention is to first provide a substrate 2 0 with a memory cell array region 2 0 2 and a peripheral circuit region 2 0 3, and dielectrics have been sequentially formed on the substrate 200. Layer 204 and conductive layers (206 and 208). The material of the dielectric layer 204 is, for example, silicon oxide, the material of the conductive layer 206 is, for example, polycrystalline stone, and the material of the conductive layer 208 is, for example, petrochemical metal, and the petrochemical metal is, for example, It's Shixi Iron. In addition, when the material of the dielectric layer 204 is, for example, oxidized silicon, the method of forming it is, for example, a thermal oxidation method, and the conductive layer (206 and

11639t.wf.ptd 第13頁 1220768 五、發明說明（7) 2 0 8 )的形成方法例如是化學氣相沈積法。之後，於導電層208上形成圖案化之罩幕層210。其中，罩幕層2 1 0的材質例如是氮化石夕，且其形成方法例如是先於基底2 0 0上沈積一層氮化矽，然後再利用習知之圖案化的技術來定義出所欲形成之圖案。接著，請參照第3 B圖，以罩幕層2 1 0為蝕刻罩幕，進行蝕刻製程，以移除導電層2 0 8，直至導電層2 0 6之表面裸露出來為止，而形成圖案化之導電層208a ，其中蝕刻製程例如進行習知之圖案化的步驟。此處值得注意的是，由於記憶胞陣列區2 0 2中所欲定義之閘極的分布密度大於周邊電路區2 0 3中所欲定義之閘極的分布密度。如此會造成此二區域（2 0 2與2 0 3 )之蝕刻速度不同，而使得當周邊電路區203已裸露出導電層206時，記憶胞陣列區2 0 2中仍有未蝕刻完全的導電層2 0 8 b。然後，請參照第3 C圖，進行另一次的蝕刻製程，以移除導電層2 0 8 a側壁之部分厚度以形成内縮的導電層2 0 8 c，並且將上述步驟中之未蝕刻完全的導電層2 0 8 b同時移除。其中，此蝕刻製程例如是濕式蝕刻，且此濕式蝕刻製程係以R C A 1作為钱刻液來進行之，而此R C A 1钱刻液係由氨水 (ΝΗ40Η)、雙氧水（H2 02 )與去離子水所構成。由於RCA1蝕刻液對於導電層（208a與208b)之蝕刻選擇比大於對導電層 2 0 6之蝕刻選擇比，所以在此蝕刻製程中，在幾乎不對周邊電路區2 0 3之導電層2 0 6表面進行蝕刻的情況下，可以將記憶胞陣列區2 0 2殘留之導電層2 0 8 b去除，並同時移除記11639t.wf.ptd Page 13 1220768 V. Description of the invention (7) 2 0 8) The formation method is, for example, a chemical vapor deposition method. Thereafter, a patterned mask layer 210 is formed on the conductive layer 208. The material of the mask layer 2 10 is, for example, nitride nitride, and the formation method is, for example, depositing a layer of silicon nitride on the substrate 200, and then using the conventional patterning technology to define the desired formation pattern. Next, referring to FIG. 3B, an etching process is performed using the mask layer 2 10 as an etching mask to remove the conductive layer 208 until the surface of the conductive layer 206 is exposed to form a pattern. For the conductive layer 208a, the etching process is performed, for example, a conventional patterning step. It is worth noting here that the distribution density of the gates to be defined in the memory cell array region 202 is larger than the distribution density of the gates to be defined in the peripheral circuit region 203. This will cause the etching speeds of these two areas (202 and 2003) to be different, so that when the conductive layer 206 is exposed in the peripheral circuit area 203, the conductive area in the memory cell array area 202 is still not fully etched. Layer 2 0 8 b. Then, referring to FIG. 3C, another etching process is performed to remove a part of the thickness of the sidewall of the conductive layer 208a to form a contracted conductive layer 208c. The conductive layer 2 0 8 b is removed at the same time. The etching process is, for example, wet etching, and the wet etching process is performed by using RCA 1 as the etching solution, and the RCA 1 etching solution is composed of ammonia (NΗ40Η), hydrogen peroxide (H2 02), and Made of ionized water. Since the etching selection ratio of the RCA1 etching solution to the conductive layers (208a and 208b) is larger than the etching selection ratio to the conductive layer 206, in this etching process, the conductive layer 2 0 6 of the peripheral circuit area 2 0 3 is hardly When the surface is etched, the conductive layer 2 0 8 b remaining in the memory cell array region 2 02 can be removed, and the memory can be removed at the same time.

11639twf.ptd 第14頁 1220768 五、發明說明（8) 憶胞陣列區2 0 2與周邊電路區2 0 3之導電層2 0 8 a側壁之部分厚度，從而使得兩區202、203的導電層206具有相近的厚度。繼之，請參照第3 D圖，進行熱製程，以使導電層2 0 8 c 中的晶格重新排列，並且藉由此熱製程穩定導電層2 0 8 c的性質。其中，熱製程例如是快速熱回火製程（R T A )。而且，在熱製程的過程中，導電層2 0 8 c會因晶粒的成長而造成側面凸起，而將原本凹陷的部分填滿以形成導電層 2 0 8 d ° 隨後，請參照第3 E圖，以罩幕層2 1 0為蝕刻罩幕，進行再一次蝕刻製程，以移除導電層2 0 6，直到記憶胞陣列區202與周邊電路區203的介電層204之表面裸露出來為止，而形成複數個由介電層204、導電層206a、導電層 2 0 8 d所構成的閘極結構2 1 1。其中，此蝕刻製程例如是乾式蝕刻。值得一提的是，若在第3 D圖之熱製程中，導電層2 0 8 d 超出原本之凹陷處，則在蝕刻導電層2 0 6的過程中，亦可以藉由此蝕刻製程同時將側壁之突起物一同去除。當然，在定義出閘極結構2 1 1之後，更可進行下述之第3 F圖至第3 Η圖的步驟，以在記憶胞陣列區2 0 2中形成接觸窗開口。請參照第3 F圖，進行另一次的熱製程，以在閘極結構 211的側壁與裸露之介電層204上形成襯層214。其中，所形成之襯層2 1 4例如是氧化矽。11639twf.ptd Page 14 1220768 V. Description of the invention (8) Partial thickness of the conductive layer 2 0 a of the memory cell array region 2 0 2 and peripheral circuit region 2 0 3, so that the conductive layers of the two regions 202, 203 206 has a similar thickness. Next, referring to FIG. 3D, a thermal process is performed to rearrange the crystal lattice in the conductive layer 208c, and to stabilize the properties of the conductive layer 208c by the thermal process. Among them, the thermal process is, for example, a rapid thermal tempering process (RTA). Moreover, during the thermal process, the conductive layer 2 8 c will cause side protrusions due to the growth of the crystal grains, and the originally recessed portion will be filled to form the conductive layer 2 0 8 d ° Subsequently, please refer to Section 3 In E, the mask layer 2 10 is used as an etching mask, and an etching process is performed again to remove the conductive layer 2 06 until the surfaces of the dielectric layer 204 of the memory cell array region 202 and the peripheral circuit region 203 are exposed. So far, a plurality of gate structures 2 1 1 composed of a dielectric layer 204, a conductive layer 206a, and a conductive layer 208d are formed. The etching process is, for example, dry etching. It is worth mentioning that if the conductive layer 208 d exceeds the original depression during the thermal process of FIG. 3D, the etching process of the conductive layer 206 can also be performed at the same time by this etching process. The protrusions on the side walls are removed together. Of course, after the gate structure 2 1 1 is defined, the steps from FIG. 3 F to FIG. 3 (following) can be further performed to form a contact window opening in the memory cell array area 202. Referring to FIG. 3F, another thermal process is performed to form a liner 214 on the sidewall of the gate structure 211 and the exposed dielectric layer 204. Among them, the formed lining layer 2 1 4 is, for example, silicon oxide.

11639twf.ptd 第15頁 1220768 五、發明說明（9) 接著，請參照第3 G圖，在閘極結構2 1 1以及罩幕層2 1 0 之側壁形成間隙壁2 1 8。形成間隙壁2 1 8之方法例如是先在閘極結構2 1 1表面形成氮化石夕層（未繪示），之後，再以非等向性蝕刻氮化矽層，即形成氮化矽間隙壁2 1 8。隨後，請參照第3 Η圖，在基底2 0 0上方形成絕緣層 2 2 0，其形成方法例如是先沈積一絕緣材料層（未繪示），此絕緣材料例如是氧化矽。之後，圖案化絕緣材料層。其中，在記憶胞陣列區2 0 2中相鄰的二閘極結構2 1 1之間係形成一自動對準接觸窗開口 2 2 2。後續，更可再於接觸窗開口 2 2 2中填入金屬材料（未繪示），以形成接觸窗，以使基底2 0 0中之摻雜區與後續所形成之位元線電性連接。在上述較佳實施例中，其中熱製程（快速熱回火製程）是在對導電層2 0 8 a的側壁進行蝕刻之後進行，然而本發明並不限定於此，本發明亦可以在以第一次的蝕刻製程蝕刻導電層2 0 8後，先進行熱製程，然後再以例如是濕式蝕刻法進行導電層2 0 8 a的側壁蝕刻。由於在本發明中，第一次的蝕刻製程只蝕刻至導電層 206表面，之後利用對於導電層（208a與208b)(矽化金屬層）與導電層2 0 6 (多晶石夕層）具有高钱刻選擇比的濕式#刻製程，而能夠在幾乎不對導電層2 0 6進行蝕刻的情況下，將記憶胞陣列區2 0 2中未蝕刻完全的導電層2 0 8 b去除，並同時移除兩區（202與203)之導電層208a側壁之部分厚度，因此兩區之導電層2 0 6的厚度相近，從而能夠避免習知周11639twf.ptd Page 15 1220768 V. Description of the invention (9) Next, referring to FIG. 3G, a gap wall 2 1 8 is formed on the side wall of the gate structure 2 1 1 and the cover layer 2 1 0. The method for forming the spacer 2 1 8 is, for example, first forming a nitride nitride layer (not shown) on the surface of the gate structure 2 1 1, and then etching the silicon nitride layer with anisotropy to form a silicon nitride gap. Wall 2 1 8. Subsequently, referring to FIG. 3, an insulating layer 220 is formed over the substrate 200. The method of forming the insulating layer 220 is, for example, first depositing an insulating material layer (not shown), and the insulating material is silicon oxide, for example. After that, the insulating material layer is patterned. Among them, an automatic alignment contact window opening 2 2 2 is formed between two adjacent gate structures 2 1 1 in the memory cell array area 202. Subsequently, a metal material (not shown) may be further filled into the contact window opening 2 2 2 to form a contact window, so that the doped region in the substrate 200 is electrically connected to the bit lines formed subsequently. . In the above preferred embodiment, the thermal process (rapid thermal tempering process) is performed after the sidewall of the conductive layer 208a is etched. However, the present invention is not limited to this. After the conductive layer 208 is etched by a single etching process, a thermal process is performed first, and then a sidewall etching of the conductive layer 208a is performed by, for example, a wet etching method. Because in the present invention, the first etching process only etches to the surface of the conductive layer 206, and then uses the conductive layer (208a and 208b) (silicided metal layer) and the conductive layer 206 (polycrystalline stone layer) to have high performance. Qian Ke selects the ratio of the wet-type # engraving process, and can remove the incompletely etched conductive layer 2 0 8 b in the memory cell array region 2 0 2 with almost no etching of the conductive layer 2 6, and simultaneously Part of the thickness of the side walls of the conductive layer 208a in the two regions (202 and 203) is removed, so the thickness of the conductive layer 206 in the two regions is similar, thereby avoiding the habituation week

11639twf.ptd 第16頁 1220768 五、發明說明（ίο) 邊電路區的導電層厚度較薄，而於蝕刻製程中損害到基底表面的問題。而且，利用本發明之方法，係能夠使得在移除預定移除部分之導電層208a後，所預定移除部分之導電層206具有相近的厚度，因此後續製程所需移除的導電層2 0 6厚度相近，且蝕刻終點亦容易偵測，從而能夠有效提高製程的裕度。另外，本發明在未圖案化導電層2 0 6之前就先進行熱製程，以使導電層2 0 8 c之晶格可以重新棑列，並藉此穩定其性質，由於此時導電層2 0 6尚為一整層的結構，因此習知因熱製程所產生之應力並不會對導電層206產生影響，而能夠避免習知導電層2 0 6 a因為對導電層2 0 8 c進行熱製程所產生之形變的問題，進而能夠避免在後續的接觸窗製程中產生插塞與閘極短路的問題。此外，由於本發明在進行導電層2 0 8 c的熱製程後還會進行導電層2 0 6的蝕刻製程，所以，即使熱製程造成導電層2 0 8 d的側壁突出，亦能夠藉由蝕刻導電層2 0 6的蝕刻製程將之去除，而能夠避免開口縮小的問題，並同樣能夠避免在後續的接觸窗製程中產生插塞與閘極短路的問題。雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍内，當可作些許之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。11639twf.ptd Page 16 1220768 V. Description of the Invention (ίο) The thickness of the conductive layer in the side circuit area is thin, and the substrate surface is damaged during the etching process. Moreover, by using the method of the present invention, after the conductive layer 208a of the predetermined removal portion is removed, the conductive layer 206 of the predetermined removal portion has a similar thickness, so the conductive layer 20 to be removed in subsequent processes is required. 6 The thickness is similar, and the end point of the etching is easy to detect, which can effectively improve the margin of the process. In addition, in the present invention, the thermal process is performed before the patterning of the conductive layer 206, so that the lattice of the conductive layer 208c can be re-queued, thereby stabilizing its properties. 6 is still a whole layer structure, so it is known that the stress generated by the thermal process will not affect the conductive layer 206, and the conventional conductive layer 2 0 6 a can be avoided because the conductive layer 2 0 8 c is heated. The problem of deformation caused by the manufacturing process can further avoid the problem of plug and gate short circuit in the subsequent contact window manufacturing process. In addition, since the present invention also performs an etching process of the conductive layer 206 after the thermal process of the conductive layer 208c, even if the thermal processing process causes the sidewall of the conductive layer 208d to protrude, the etching can be performed by etching. The conductive layer 206 is removed by the etching process, which can avoid the problem of shrinking the opening, and can also avoid the problem of plug and gate short circuit in the subsequent contact window process. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

11639twf.ptd 第17頁 1220768 圖式簡單說明第1 A圖至第1 E圖是習知一種閘極的製造流程剖面示意圖。第2圖是利用習知利用熱製程而造成多晶矽層扭曲形變之剖面示意圖。第3 A圖至第3 E圖是依照本發明之一較佳實施例的一種閘極的製造流程剖面示意圖。第3 F圖至第3 Η圖是依照本發明之一較佳實施例的一種接觸窗開口的製造流程剖面示意圖。【圖式標記說明】 1 00、2 0 0 :基底 1 0 2、2 0 2 :記憶胞陣列區 103、203 :周邊電路區 1 04、2 0 4 :介電層 1 0 6 、1 0 6 a :多晶矽層 108、108a、108b、108c :矽化金屬層 1 1 0、2 1 0 ··罩幕層 1 1 2 a、1 1 2 b :閘極 1 1 4 ··襯氧化層 206 、206a 、208 、208a 、208b 、208c 、208d :導電層 2 1 1 :閘極結構 2 1 4 :襯層 2 1 8 :間隙壁 2 2 0 :絕緣層 2 2 2 :接觸窗開口11639twf.ptd Page 17 1220768 Brief description of drawings Figures 1A to 1E are schematic cross-sectional views of a conventional manufacturing process of a gate electrode. Figure 2 is a schematic cross-sectional view of the distortion and deformation of a polycrystalline silicon layer caused by a conventional thermal process. 3A to 3E are schematic cross-sectional views illustrating a manufacturing process of a gate electrode according to a preferred embodiment of the present invention. 3F to 3D are schematic cross-sectional views illustrating a manufacturing process of a contact window opening according to a preferred embodiment of the present invention. [Illustration of figure mark] 1 00, 2 0 0: substrate 1 0 2, 2 0 2: memory cell array area 103, 203: peripheral circuit area 1 04, 2 0 4: dielectric layer 1 0 6, 1 0 6 a: polycrystalline silicon layers 108, 108a, 108b, 108c: silicided metal layers 1 1 0, 2 1 0 · mask layer 1 1 2 a, 1 1 2 b: gate 1 1 4 · lining oxide layers 206, 206a , 208, 208a, 208b, 208c, 208d: conductive layer 2 1 1: gate structure 2 1 4: lining layer 2 1 8: partition wall 2 2 0: insulating layer 2 2 2: contact window opening

11639twf.ptd 第18頁11639twf.ptd Page 18

Claims

1220768 六、申請專利範圍 1 · 一種閘極的製造方法，包括：提供具有一記憶胞陣列區與一周邊電路區之一基底，且該基底上已依序形成有一介電層、一第一導電層以及一第二導電層；於該第二導電層上形成圖案化之一罩幕層；以該罩幕層為钱刻罩幕，進行一第一钱刻製程，以移除該第二導電層，直到該記憶胞陣列區與該周邊電路區其中之一的該第一導電層之表面裸露出來為止；進行一第二蝕刻製程，以移除該第二導電層側壁之部分厚度，其中該第二蝕刻製程對於該第二導電層之蝕刻選擇比大於對該第一導電層之蝕刻選擇比；進行一第一熱製程；以及以該罩幕層為蝕刻罩幕，進行一第三蝕刻製程，以移除該第一導電層，直到該記憶胞陣列區與該周邊電路區的該介電層之表面裸露出來為止。 2. 如申請專利範圍第1項所述之閘極的製造方法，其中該第二I虫刻製程包括進行一濕式餘刻製程。 3. 如申請專利範圍第2項所述之閘極的製造方法，其中該濕式蝕刻製程所使用之蝕刻液包括一 R C A 1蝕刻液，且該RCA1餘刻液係由氨水（ΝΗ40Η)、雙氧水（H202 )與去離子水所構成。 4 ·如申請專利範圍第1項所述之閘極的製造方法，其中該第一熱製程係進行於該第一蝕刻製程之後與該第二蝕刻製程之前。1220768 VI. Application Patent Scope 1. A method for manufacturing a gate electrode, comprising: providing a substrate having a memory cell array region and a peripheral circuit region, and a dielectric layer and a first conductive layer have been sequentially formed on the substrate; Layer and a second conductive layer; forming a patterned mask layer on the second conductive layer; using the mask layer as a money engraving mask, performing a first money engraving process to remove the second conductive layer Layer until the surface of the first conductive layer in one of the memory cell array area and the peripheral circuit area is exposed; performing a second etching process to remove a part of the thickness of the side wall of the second conductive layer, wherein the The etching selection ratio of the second etching process for the second conductive layer is greater than the etching selection ratio of the first conductive layer; a first thermal process is performed; and a third etching process is performed using the mask layer as an etching mask. To remove the first conductive layer until the surfaces of the dielectric layer of the memory cell array region and the peripheral circuit region are exposed. 2. The method for manufacturing a gate electrode as described in item 1 of the scope of patent application, wherein the second I-etching process includes performing a wet-remaining process. 3. The gate electrode manufacturing method as described in item 2 of the scope of patent application, wherein the etching solution used in the wet etching process includes an RCA 1 etching solution, and the remaining RCA 1 etching solution is composed of ammonia water (NΗ40Η) and hydrogen peroxide water. (H202) and deionized water. 4. The gate manufacturing method according to item 1 of the scope of patent application, wherein the first thermal process is performed after the first etching process and before the second etching process.

11639t.wf.ptd 第19頁 1220768 六、申請專利範圍 5 ·如申請專利範圍第1項所述之閘極的製造方法，其中該第一導電層包括一多晶石夕層。 6 .如申請專利範圍苐1項所述之閘極的製造方法，其中該第二導電層包括一矽化金屬層。 7 .如申請專利乾圍第6項所述之閘極的製造方法，其中該矽化金屬層的材質包括矽化鎢。 8 ·如申請專利範圍第1項所述之閘極的製造方法，其中該第一熱製程包括快速熱回火製程。 9 ·如申請專利範圍第1項所述之閘極的製造方法，其中在該第三蝕刻製程之後，更包括進行一第二熱製程，以在該開口的側壁與裸露之該介電層上形成一襯層。 1 0 .如申請專利範圍第9項所述之閘極的製造方法，其中該第二熱製程包括快速熱氧化製程。 11. 一種接觸窗口的製造方法，包括：提供具有一記憶胞陣列區與一周邊電路區之一基底，且該基底上已依序形成有一介電層、一第一導電層以及一第二導電層；於該第二導電層上形成圖案化之一罩幕層；以該罩幕層為餘刻罩幕，進行一第一钱刻製程，以移除該第二導電層，直到該記憶胞陣列區與該周邊電路區其中之一的該第一導電層之表面裸露出來為止；進行一第二蝕刻製程，以移除該第二導電層側壁之部分厚度，其中該第二蝕刻製程對於該第二導電層之蝕刻選擇比大於對該第一導電層之蝕刻選擇比；11639t.wf.ptd Page 19 1220768 6. Scope of Patent Application 5 • The method for manufacturing a gate electrode as described in item 1 of the scope of patent application, wherein the first conductive layer includes a polycrystalline stone layer. 6. The method for manufacturing a gate electrode according to item 1 of the scope of patent application, wherein the second conductive layer includes a silicided metal layer. 7. The method for manufacturing a gate electrode according to item 6 of the patent application, wherein the material of the silicided metal layer includes tungsten silicide. 8 The method for manufacturing a gate electrode as described in item 1 of the scope of patent application, wherein the first thermal process includes a rapid thermal tempering process. 9 · The method for manufacturing a gate electrode according to item 1 of the scope of patent application, wherein after the third etching process, a second thermal process is further performed to place the sidewall of the opening and the exposed dielectric layer. A liner is formed. 10. The method for manufacturing a gate electrode according to item 9 of the scope of patent application, wherein the second thermal process includes a rapid thermal oxidation process. 11. A method for manufacturing a contact window, comprising: providing a substrate having a memory cell array region and a peripheral circuit region, and a dielectric layer, a first conductive layer and a second conductive layer have been sequentially formed on the substrate. Layer; forming a patterned mask layer on the second conductive layer; using the mask layer as the remaining mask, performing a first money engraving process to remove the second conductive layer until the memory cell The surface of the first conductive layer in one of the array region and the peripheral circuit region is exposed; a second etching process is performed to remove a part of the thickness of the side wall of the second conductive layer, and the second etching process is for the An etching selection ratio of the second conductive layer is greater than an etching selection ratio of the first conductive layer;

11639twf.ptd 第20頁 1220768 六、申請專利範圍進行一第一熱製程；以該罩幕層為#刻罩幕，進行一第三钱刻製程，以移除該第一導電層，直到該記憶胞陣列區與該周邊電路區的該介電層之表面裸露出來為止，以形成複數個閘極結構；進行一第二熱製程，以在該些閘極結構的側壁與裸露之該介電層上形成一概層；於該基底上方形成一絕緣層，以覆蓋該些閘極結構；以及圖案化該絕緣層，以在相鄰之其中二該些閘極結構之間形成一接觸窗開口。 1 2 ·如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中在進行該第二熱製程的步驟之後與於該基底上方形成該絕緣層之前，更包括於該些閘極結構之側壁形成一間隙壁。 1 3 .如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中該第二蝕刻製程包括進行一濕式蝕刻製程。 1 4.如申請專利範圍第1 3項所述之接觸窗口的製造方法，其中該濕式蝕刻製程所使用之蝕刻液包括一 RC A 1蝕刻液，且該RCA1蝕刻液係由氨水（ΝΗ40Η)、雙氧水（H2 02 )與去離子水所構成。 1 5.如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中該第一熱製程係進行於該第一蝕刻製程之後與該第二蝕刻製程之前。 1 6 .如申請專利範圍第1 1項所述之接觸窗口的製造方11639twf.ptd Page 20 1220768 6. The scope of patent application is to perform a first thermal process; the mask layer is #etched mask, and a third money engraving process is performed to remove the first conductive layer until the memory Until the surface of the dielectric layer of the cell array region and the peripheral circuit region is exposed to form a plurality of gate structures; a second thermal process is performed to expose the dielectric layers on the sidewalls of the gate structures and the exposed dielectric layer Forming a general layer on the substrate; forming an insulating layer over the substrate to cover the gate structures; and patterning the insulating layer to form a contact window opening between two adjacent gate structures. 1 2 · The method for manufacturing a contact window as described in item 11 of the scope of patent application, wherein after the step of performing the second thermal process and before forming the insulating layer over the substrate, the gate structure is further included. A sidewall is formed on the side wall. 13. The method for manufacturing a contact window according to item 11 of the scope of patent application, wherein the second etching process includes performing a wet etching process. 14. The method for manufacturing a contact window as described in item 13 of the scope of patent application, wherein the etching solution used in the wet etching process includes an RC A 1 etching solution, and the RCA1 etching solution is made of ammonia (NΗ40Η). , Hydrogen peroxide (H2 02) and deionized water. 1 5. The method for manufacturing a contact window according to item 11 of the scope of patent application, wherein the first thermal process is performed after the first etching process and before the second etching process. 16. The manufacturer of the contact window as described in item 11 of the scope of patent application

11639twf.ptd 第21頁 1220768 六、申請專利範圍法，其中該第一導電層包括一多晶矽層如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中該第二導電層包括一石夕化金屬層。 1 8 ·如申請專利範圍第1 7項所述之接觸窗口的製造方法，其中該石夕化金屬層的材質包括石夕化鶬。 1 9 .如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中該第一熱製程包括快速熱回火製程。 2 0 .如申請專利範圍第1 1項所述之接觸窗口的製造方法，其中該第二熱製程包括快速熱氧化製程。11639twf.ptd Page 21 1220768 VI. Patent application method, wherein the first conductive layer includes a polycrystalline silicon layer, a method for manufacturing a contact window as described in item 11 of the patent application scope, wherein the second conductive layer includes a stone Chemical metal layer. 18 · The method for manufacturing a contact window as described in item 17 of the scope of patent application, wherein the material of the petrified metal layer includes petrium. 19. The method for manufacturing a contact window according to item 11 of the scope of patent application, wherein the first thermal process includes a rapid thermal tempering process. 20. The method for manufacturing a contact window according to item 11 of the scope of patent application, wherein the second thermal process includes a rapid thermal oxidation process.

11639twf.ptd 第22頁11639twf.ptd Page 22