SG144135A1 - Multi-chips package and method of forming the same - Google Patents
Multi-chips package and method of forming the sameInfo
- Publication number
- SG144135A1 SG144135A1 SG200800131-5A SG2008001315A SG144135A1 SG 144135 A1 SG144135 A1 SG 144135A1 SG 2008001315 A SG2008001315 A SG 2008001315A SG 144135 A1 SG144135 A1 SG 144135A1
- Authority
- SG
- Singapore
- Prior art keywords
- rdl
- die
- dielectric layer
- forming
- formed under
- Prior art date
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Wire Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
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Families Citing this family (137)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6710454B1 (en) * | 2000-02-16 | 2004-03-23 | Micron Technology, Inc. | Adhesive layer for an electronic apparatus having multiple semiconductor devices |
US8959762B2 (en) | 2005-08-08 | 2015-02-24 | Rf Micro Devices, Inc. | Method of manufacturing an electronic module |
US7451539B2 (en) * | 2005-08-08 | 2008-11-18 | Rf Micro Devices, Inc. | Method of making a conformal electromagnetic interference shield |
US8053872B1 (en) | 2007-06-25 | 2011-11-08 | Rf Micro Devices, Inc. | Integrated shield for a no-lead semiconductor device package |
US20090002969A1 (en) | 2007-06-27 | 2009-01-01 | Rf Micro Devices, Inc. | Field barrier structures within a conformal shield |
US8062930B1 (en) | 2005-08-08 | 2011-11-22 | Rf Micro Devices, Inc. | Sub-module conformal electromagnetic interference shield |
US8049323B2 (en) * | 2007-02-16 | 2011-11-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip holder with wafer level redistribution layer |
US9601412B2 (en) * | 2007-06-08 | 2017-03-21 | Cyntec Co., Ltd. | Three-dimensional package structure |
TWI335059B (en) * | 2007-07-31 | 2010-12-21 | Siliconware Precision Industries Co Ltd | Multi-chip stack structure having silicon channel and method for fabricating the same |
US7777300B2 (en) * | 2007-09-18 | 2010-08-17 | Infineon Technologies Ag | Semiconductor device with capacitor |
TWI360207B (en) | 2007-10-22 | 2012-03-11 | Advanced Semiconductor Eng | Chip package structure and method of manufacturing |
US7956453B1 (en) * | 2008-01-16 | 2011-06-07 | Amkor Technology, Inc. | Semiconductor package with patterning layer and method of making same |
US8247267B2 (en) | 2008-03-11 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wafer level IC assembly method |
TWI387077B (zh) * | 2008-06-12 | 2013-02-21 | Chipmos Technologies Inc | 晶粒重新配置之封裝結構及其方法 |
US8076180B2 (en) * | 2008-07-07 | 2011-12-13 | Infineon Technologies Ag | Repairable semiconductor device and method |
TWI573201B (zh) | 2008-07-18 | 2017-03-01 | 聯測總部私人有限公司 | 封裝結構性元件 |
FI122217B (fi) * | 2008-07-22 | 2011-10-14 | Imbera Electronics Oy | Monisirupaketti ja valmistusmenetelmä |
US20100122456A1 (en) * | 2008-11-17 | 2010-05-20 | Chen-Hua Yu | Integrated Alignment and Bonding System |
US20100133682A1 (en) * | 2008-12-02 | 2010-06-03 | Infineon Technologies Ag | Semiconductor device |
US7943421B2 (en) * | 2008-12-05 | 2011-05-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Component stacking using pre-formed adhesive films |
US8119454B2 (en) * | 2008-12-08 | 2012-02-21 | Stmicroelectronics Asia Pacific Pte Ltd. | Manufacturing fan-out wafer level packaging |
CN101866892B (zh) * | 2009-04-20 | 2011-12-07 | 财团法人工业技术研究院 | 芯片的布局结构与方法 |
JP2010262992A (ja) * | 2009-04-30 | 2010-11-18 | Sanyo Electric Co Ltd | 半導体モジュールおよび携帯機器 |
WO2011017202A2 (en) * | 2009-08-06 | 2011-02-10 | Rambus Inc. | Packaged semiconductor device for high performance memory and logic |
KR101620347B1 (ko) * | 2009-10-14 | 2016-05-13 | 삼성전자주식회사 | 패시브 소자들이 실장된 반도체 패키지 |
US8217272B2 (en) * | 2009-12-18 | 2012-07-10 | Intel Corporation | Apparatus and method for embedding components in small-form-factor, system-on-packages |
US9225379B2 (en) | 2009-12-18 | 2015-12-29 | Intel Corporation | Apparatus and method for embedding components in small-form-factor, system-on-packages |
KR101078740B1 (ko) * | 2009-12-31 | 2011-11-02 | 주식회사 하이닉스반도체 | 스택 패키지 및 그의 제조방법 |
US8115260B2 (en) * | 2010-01-06 | 2012-02-14 | Fairchild Semiconductor Corporation | Wafer level stack die package |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
US9385095B2 (en) | 2010-02-26 | 2016-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | 3D semiconductor package interposer with die cavity |
KR101695846B1 (ko) * | 2010-03-02 | 2017-01-16 | 삼성전자 주식회사 | 적층형 반도체 패키지 |
US8618654B2 (en) * | 2010-07-20 | 2013-12-31 | Marvell World Trade Ltd. | Structures embedded within core material and methods of manufacturing thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US8274149B2 (en) * | 2010-03-29 | 2012-09-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package having a buffer structure and method of fabricating the same |
US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US8847376B2 (en) | 2010-07-23 | 2014-09-30 | Tessera, Inc. | Microelectronic elements with post-assembly planarization |
TWI426587B (zh) * | 2010-08-12 | 2014-02-11 | 矽品精密工業股份有限公司 | 晶片尺寸封裝件及其製法 |
US9137934B2 (en) | 2010-08-18 | 2015-09-15 | Rf Micro Devices, Inc. | Compartmentalized shielding of selected components |
CN102117799B (zh) * | 2010-11-25 | 2013-01-23 | 日月光半导体制造股份有限公司 | 埋入型多芯片半导体封装结构及其制造方法 |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8619431B2 (en) * | 2010-12-22 | 2013-12-31 | ADL Engineering Inc. | Three-dimensional system-in-package package-on-package structure |
US8835226B2 (en) | 2011-02-25 | 2014-09-16 | Rf Micro Devices, Inc. | Connection using conductive vias |
US9627230B2 (en) | 2011-02-28 | 2017-04-18 | Qorvo Us, Inc. | Methods of forming a microshield on standard QFN package |
US20120281113A1 (en) * | 2011-05-06 | 2012-11-08 | Raytheon Company | USING A MULTI-CHIP SYSTEM IN A PACKAGE (MCSiP) IN IMAGING APPLICATIONS TO YIELD A LOW COST, SMALL SIZE CAMERA ON A CHIP |
TWI455280B (zh) * | 2011-07-19 | 2014-10-01 | 矽品精密工業股份有限公司 | 半導體封裝件 |
US9312214B2 (en) * | 2011-09-22 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor packages having polymer-containing substrates and methods of forming same |
US9679863B2 (en) | 2011-09-23 | 2017-06-13 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming interconnect substrate for FO-WLCSP |
US9190391B2 (en) * | 2011-10-26 | 2015-11-17 | Maxim Integrated Products, Inc. | Three-dimensional chip-to-wafer integration |
KR101923531B1 (ko) | 2011-12-23 | 2018-11-30 | 삼성전자주식회사 | 반도체 칩 본딩 장치 |
TWI474444B (zh) * | 2011-12-28 | 2015-02-21 | Princo Corp | 超薄多層基板之封裝方法 |
KR101394203B1 (ko) | 2011-12-29 | 2014-05-14 | 주식회사 네패스 | 적층형 반도체 패키지 및 그 제조 방법 |
US9171823B2 (en) * | 2011-12-30 | 2015-10-27 | Stmicroelectronics Pte Ltd | Circuit module with multiple submodules |
US9691706B2 (en) * | 2012-01-23 | 2017-06-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-chip fan out package and methods of forming the same |
US8648473B2 (en) * | 2012-03-27 | 2014-02-11 | Infineon Technologies Ag | Chip arrangement and a method for forming a chip arrangement |
US8922005B2 (en) * | 2012-04-11 | 2014-12-30 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for package on package devices with reversed stud bump through via interconnections |
US8698323B2 (en) * | 2012-06-18 | 2014-04-15 | Invensas Corporation | Microelectronic assembly tolerant to misplacement of microelectronic elements therein |
US8878360B2 (en) * | 2012-07-13 | 2014-11-04 | Intel Mobile Communications GmbH | Stacked fan-out semiconductor chip |
US9117715B2 (en) * | 2012-07-18 | 2015-08-25 | Hong Kong Applied Science and Technology Research Institute Company Limited | Wafer-level device packaging |
US9136213B2 (en) | 2012-08-02 | 2015-09-15 | Infineon Technologies Ag | Integrated system and method of making the integrated system |
US8872349B2 (en) | 2012-09-11 | 2014-10-28 | Intel Corporation | Bridge interconnect with air gap in package assembly |
US9209156B2 (en) | 2012-09-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional integrated circuits stacking approach |
KR101909202B1 (ko) | 2012-10-08 | 2018-10-17 | 삼성전자 주식회사 | 패키지-온-패키지 타입의 패키지 |
US9263511B2 (en) * | 2013-02-11 | 2016-02-16 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package with metal-insulator-metal capacitor and method of manufacturing the same |
TWI517328B (zh) | 2013-03-07 | 2016-01-11 | 矽品精密工業股份有限公司 | 半導體裝置 |
US9147663B2 (en) * | 2013-05-28 | 2015-09-29 | Intel Corporation | Bridge interconnection with layered interconnect structures |
US9807890B2 (en) | 2013-05-31 | 2017-10-31 | Qorvo Us, Inc. | Electronic modules having grounded electromagnetic shields |
CN103390717B (zh) * | 2013-07-30 | 2016-02-03 | 广东洲明节能科技有限公司 | 叠层led发光模组及制作方法 |
KR20150025129A (ko) * | 2013-08-28 | 2015-03-10 | 삼성전기주식회사 | 전자 소자 모듈 및 그 제조 방법 |
CN103594451B (zh) * | 2013-11-18 | 2016-03-16 | 华进半导体封装先导技术研发中心有限公司 | 多层多芯片扇出结构及制作方法 |
KR101612220B1 (ko) * | 2015-02-23 | 2016-04-12 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지 |
TWI556379B (zh) * | 2014-01-02 | 2016-11-01 | 矽品精密工業股份有限公司 | 半導體封裝件及其製法 |
US9653442B2 (en) * | 2014-01-17 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit package and methods of forming same |
US9653443B2 (en) | 2014-02-14 | 2017-05-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thermal performance structure for semiconductor packages and method of forming same |
US10056267B2 (en) | 2014-02-14 | 2018-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design for semiconductor packages and method of forming same |
US9443815B2 (en) * | 2014-02-21 | 2016-09-13 | Maxim Integrated Products, Inc. | Embedded die redistribution layers for active device |
JP2015216263A (ja) * | 2014-05-12 | 2015-12-03 | マイクロン テクノロジー, インク. | 半導体装置 |
US9595485B2 (en) * | 2014-06-26 | 2017-03-14 | Nxp Usa, Inc. | Microelectronic packages having embedded sidewall substrates and methods for the producing thereof |
TWI566348B (zh) * | 2014-09-03 | 2017-01-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
US9443780B2 (en) * | 2014-09-05 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having recessed edges and method of manufacture |
TWI569368B (zh) * | 2015-03-06 | 2017-02-01 | 恆勁科技股份有限公司 | 封裝基板、包含該封裝基板的封裝結構及其製作方法 |
US9659907B2 (en) | 2015-04-07 | 2017-05-23 | Apple Inc. | Double side mounting memory integration in thin low warpage fanout package |
KR102368070B1 (ko) * | 2015-04-13 | 2022-02-25 | 삼성전자주식회사 | 반도체 패키지 |
US10373922B2 (en) | 2015-06-04 | 2019-08-06 | Micron Technology, Inc. | Methods of manufacturing a multi-device package |
JP6773367B2 (ja) * | 2015-06-25 | 2020-10-21 | インテル・コーポレーション | パッケージオンパッケージのため凹型導電性コンタクトを有する集積回路構造及び方法 |
KR102505189B1 (ko) * | 2015-07-22 | 2023-03-02 | 인텔 코포레이션 | 다층 패키지 |
US9401350B1 (en) * | 2015-07-29 | 2016-07-26 | Qualcomm Incorporated | Package-on-package (POP) structure including multiple dies |
CN105514071B (zh) * | 2016-01-22 | 2019-01-25 | 中芯长电半导体(江阴)有限公司 | 一种扇出型芯片的封装方法及封装结构 |
CN105575913B (zh) * | 2016-02-23 | 2019-02-01 | 华天科技(昆山)电子有限公司 | 埋入硅基板扇出型3d封装结构 |
KR102522322B1 (ko) * | 2016-03-24 | 2023-04-19 | 삼성전자주식회사 | 반도체 패키지 |
DE102016110862B4 (de) | 2016-06-14 | 2022-06-30 | Snaptrack, Inc. | Modul und Verfahren zur Herstellung einer Vielzahl von Modulen |
US10734333B2 (en) * | 2016-06-15 | 2020-08-04 | Intel Corporation | Semiconductor package having inductive lateral interconnects |
US9859254B1 (en) * | 2016-06-30 | 2018-01-02 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and a manufacturing method thereof |
KR102549402B1 (ko) * | 2016-08-04 | 2023-06-28 | 삼성전자주식회사 | 반도체 패키지 및 이의 제조 방법 |
US10297551B2 (en) * | 2016-08-12 | 2019-05-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package |
EP3288076B1 (en) | 2016-08-25 | 2021-06-23 | IMEC vzw | A semiconductor die package and method of producing the package |
US10366968B2 (en) * | 2016-09-30 | 2019-07-30 | Intel IP Corporation | Interconnect structure for a microelectronic device |
US20180166356A1 (en) * | 2016-12-13 | 2018-06-14 | Globalfoundries Inc. | Fan-out circuit packaging with integrated lid |
CN106876356B (zh) * | 2017-03-09 | 2020-04-17 | 华天科技(昆山)电子有限公司 | 芯片嵌入硅基式扇出型封装结构及其制作方法 |
US10636775B2 (en) * | 2017-10-27 | 2020-04-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and manufacturing method thereof |
KR101933425B1 (ko) * | 2017-11-30 | 2018-12-28 | 삼성전기 주식회사 | 반도체 패키지 |
US10651126B2 (en) * | 2017-12-08 | 2020-05-12 | Applied Materials, Inc. | Methods and apparatus for wafer-level die bridge |
KR102061852B1 (ko) * | 2017-12-18 | 2020-01-02 | 삼성전자주식회사 | 반도체 패키지 |
KR101922885B1 (ko) * | 2017-12-22 | 2018-11-28 | 삼성전기 주식회사 | 팬-아웃 반도체 패키지 |
TWI662695B (zh) * | 2017-12-28 | 2019-06-11 | 財團法人工業技術研究院 | 晶圓級晶片尺寸封裝結構 |
CN107993994B (zh) * | 2017-12-29 | 2023-07-25 | 长鑫存储技术有限公司 | 半导体封装结构及其制造方法 |
US10672715B2 (en) * | 2018-04-16 | 2020-06-02 | Amkor Technology, Inc. | Semiconductor package using cavity substrate and manufacturing methods |
US10727203B1 (en) * | 2018-05-08 | 2020-07-28 | Rockwell Collins, Inc. | Die-in-die-cavity packaging |
US11127689B2 (en) | 2018-06-01 | 2021-09-21 | Qorvo Us, Inc. | Segmented shielding using wirebonds |
US11219144B2 (en) | 2018-06-28 | 2022-01-04 | Qorvo Us, Inc. | Electromagnetic shields for sub-modules |
KR102582422B1 (ko) * | 2018-06-29 | 2023-09-25 | 삼성전자주식회사 | 재배선층을 갖는 반도체 패키지 |
CN109148431B (zh) * | 2018-07-18 | 2020-04-17 | 华天科技(昆山)电子有限公司 | 距离传感器芯片封装结构及其晶圆级封装方法 |
US10756051B2 (en) * | 2018-09-04 | 2020-08-25 | Ningbo Semiconductor International Corporation | Wafer-level system packaging method and package structure |
SG10201809987YA (en) * | 2018-11-09 | 2020-06-29 | Delta Electronics Int’L Singapore Pte Ltd | Package structure and packaging process |
US11114363B2 (en) | 2018-12-20 | 2021-09-07 | Qorvo Us, Inc. | Electronic package arrangements and related methods |
US11515282B2 (en) | 2019-05-21 | 2022-11-29 | Qorvo Us, Inc. | Electromagnetic shields with bonding wires for sub-modules |
TWI688073B (zh) * | 2019-05-22 | 2020-03-11 | 穩懋半導體股份有限公司 | 半導體積體電路及其電路佈局方法 |
US11616048B2 (en) | 2019-06-12 | 2023-03-28 | Texas Instruments Incorporated | IC package with multiple dies |
US11380620B2 (en) | 2019-06-14 | 2022-07-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package including cavity-mounted device |
CN110491792A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种树脂型三维扇出集成封装方法及结构 |
CN110491853A (zh) * | 2019-09-16 | 2019-11-22 | 中国电子科技集团公司第五十八研究所 | 一种硅基三维扇出集成封装方法及结构 |
CN110600383A (zh) * | 2019-09-27 | 2019-12-20 | 中国电子科技集团公司第五十八研究所 | 一种2.5d硅基转接板封装方法及结构 |
CN110610868A (zh) * | 2019-09-27 | 2019-12-24 | 中国电子科技集团公司第五十八研究所 | 一种3d扇出型封装方法及结构 |
CN110828496B (zh) * | 2019-11-15 | 2022-10-11 | 华天科技(昆山)电子有限公司 | 半导体器件及其制造方法 |
US11152529B2 (en) * | 2019-12-10 | 2021-10-19 | Advanced Semiconductor Engineering, Inc. | Semicondutor package structures and methods of manufacturing the same |
CN111430310A (zh) * | 2020-04-02 | 2020-07-17 | 华天科技(昆山)电子有限公司 | 芯片内***集成封装结构及其制作方法、立体堆叠器件 |
US11605571B2 (en) * | 2020-05-29 | 2023-03-14 | Qualcomm Incorporated | Package comprising a substrate, an integrated device, and an encapsulation layer with undercut |
US11342272B2 (en) * | 2020-06-11 | 2022-05-24 | Advanced Semiconductor Engineering, Inc. | Substrate structures, and methods for forming the same and semiconductor package structures |
CN111564419B (zh) * | 2020-07-14 | 2021-01-01 | 甬矽电子(宁波)股份有限公司 | 芯片叠层封装结构、其制作方法和电子设备 |
CN212648273U (zh) | 2020-07-29 | 2021-03-02 | 隆达电子股份有限公司 | 发光二极管装置 |
US11610875B2 (en) * | 2020-09-18 | 2023-03-21 | Lextar Electronics Corporation | Light emitting array structure and display |
CN112652542B (zh) * | 2020-12-22 | 2023-06-16 | 厦门通富微电子有限公司 | 一种三维堆叠的扇出型芯片封装方法及封装结构 |
CN115050308A (zh) | 2021-03-08 | 2022-09-13 | 隆达电子股份有限公司 | 显示器 |
CN113471160A (zh) * | 2021-06-29 | 2021-10-01 | 矽磐微电子(重庆)有限公司 | 芯片封装结构及其制作方法 |
CN117751437A (zh) * | 2021-08-19 | 2024-03-22 | 华为技术有限公司 | 多芯片***及其制备方法、光接收机和终端 |
TWI800104B (zh) * | 2021-11-19 | 2023-04-21 | 欣興電子股份有限公司 | 晶片封裝結構及其製作方法 |
CN116092956B (zh) * | 2023-04-10 | 2023-11-03 | 北京华封集芯电子有限公司 | 芯片封装方法及芯片封装结构 |
Family Cites Families (5)
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JP4012496B2 (ja) * | 2003-09-19 | 2007-11-21 | カシオ計算機株式会社 | 半導体装置 |
JP4198566B2 (ja) * | 2003-09-29 | 2008-12-17 | 新光電気工業株式会社 | 電子部品内蔵基板の製造方法 |
JP4581768B2 (ja) * | 2005-03-16 | 2010-11-17 | ソニー株式会社 | 半導体装置の製造方法 |
US20080116564A1 (en) * | 2006-11-21 | 2008-05-22 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving cavity and method of the same |
US20080136004A1 (en) * | 2006-12-08 | 2008-06-12 | Advanced Chip Engineering Technology Inc. | Multi-chip package structure and method of forming the same |
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US20080157316A1 (en) | 2008-07-03 |
JP2008166824A (ja) | 2008-07-17 |
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US20080224306A1 (en) | 2008-09-18 |
DE102008003156A1 (de) | 2008-07-31 |
TW200834876A (en) | 2008-08-16 |
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