TW200834876A - Multi-chips package and method of forming the same - Google Patents

Multi-chips package and method of forming the same Download PDF

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Publication number
TW200834876A
TW200834876A TW097100205A TW97100205A TW200834876A TW 200834876 A TW200834876 A TW 200834876A TW 097100205 A TW097100205 A TW 097100205A TW 97100205 A TW97100205 A TW 97100205A TW 200834876 A TW200834876 A TW 200834876A
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Taiwan
Prior art keywords
die
rdl
dielectric layer
substrate
layer
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TW097100205A
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English (en)
Inventor
Wen-Kun Yang
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Advanced Chip Eng Tech Inc
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Publication of TW200834876A publication Critical patent/TW200834876A/zh

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  • Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

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200834876 九、發明說明： 【發明所屬之技術領域】 本發明係關於一藉备从& ^ P 糸、、先級封裝（SIP)結構，尤係指一平 板尺寸封裝（PSP)之系統級封裝。 十 【先前技術】
於半導體元件領域，分 A ii ^ ^ 件雄、度持續地增加且元件尺寸 持績地Ifg小，封裝哎诖έ士 Τ 兴H爲 次連、M支術於上述之高密度元件上，日 ^ , 者方式一陣列錫凸塊形成於晶粒表 面上，錫凸塊之構成， 了衣 ^ m Ah九 9吏用一 g錫之復合材料，經由 鋼板衣作一思欲之錫凸塊圖 分配、訊號分配、散敎、伴^、Γ 含功率 片變得更複雜B士，種…、保4及晶片支撐。當半導體晶 封m ”專統封裝方式’例如導線架封裝、軟板 封裒以及硬板封裝技術 販 之IC封裝需求。 一去應付更小尺寸、更高密度 現今之多晶粒模組或混合一 著於一機板上且密封於—外殼中路此2:，將晶粒黏 板，豆中句人夕恳、曾& 身又使用一多層基 板”中包3多層導線與界電層以三 基板傳統上以疊片技術製作，月：：=成。夕層 ,拉朴 八甲至屬導體各自形成於介 電層上，接著將之堆疊並連結。 >wsit足回被度、南性能速度需求，故而發展系統單晶 曰 J而夕日日粒杈組廣泛應用於多種 片▲合。多晶粒模組或多晶粒封震技術，提供多個 黏者未封裝積體電路(IC)( “裸晶，’）方式於一基材上， 個晶粒被”封裝”於-整個密封材料或其他聚合物，；晶 6 200834876 # - 粒模組提供-高密度模組，其於電腦主板需求面積小，夕 晶粒模組亦提供整合性功能測試之好處。 夕 更進-步，因為傳統封裝技術必須將晶圓士刀割成為個 別晶粒’再各自封裝，此技術於製程中消耗大量時間。因 為晶片封裝技術受到積體電路研發影響甚鉅，故而當電路 之面積成為必要，封裝技術亦受其影響。由於以上所述， 封裝技術由球狀矩陣（BGA)、倒裝晶片（fc_bga)、晶/尺 寸級封裝（csp)演進至今曰之晶圓尺寸級封裝（WLP)。‘‘晶 圓尺寸級封裝顧名思義，整個封裝與其晶圓上之内部連 線，义以及其他製程步‘驟，皆完成於分割（切害〇成為晶片（晶 粒）則。一般而言，當完成整個組裝製程或封裝製程後，單 個的半導體封裝於晶圓上被分開，成為多個半導體晶粒， 此晶圓尺寸級封裝具有極小面積，並具有極佳之電器特性。 晶圓尺寸級封裝技術為一種先進封裝技術，其晶粒於 晶圓上同時製造並測言式，其後將其切割分開並組裝用於表 瞻面黏著產線。因為晶圓尺寸級封裝技術利用整個晶圓，並 非使用單顆晶片或晶粒’因此於執行切削製程前，封裝與 測試業已完成，更進一步，晶圓尺寸級封裝技術之先進， 使得打線、黏晶與填充等製程可省略。使用晶圓尺寸級封 裝技術，可降低製造成本，其尺寸與晶粒相當，此一技術 可符合電子元件極小化之需求。 雖然晶圓尺寸級封裝技術有上述之優點，某些因素依 然影響此技術之接受度。例如，雖然晶圓尺寸級封裝技術， 可降低積體電路與基板連接間（增層builduplayers —重 7 200834876 佈層RDL)之熱膨脹係數（CTE)不匹配之影響，但是無法於 晶片尺寸間允許更高球數。當元件尺寸為最小，其終端接 點數將被限制。更進一步，此晶圓尺寸級封裝，一複數個 焊墊形成於半導體晶粒上作為重佈，藉由傳統重佈製程， 其中包含之重佈層，接入一陣列型態之多個金屬墊。錫球 直接熔接於金屬墊上，藉由重佈製程，其形成一陣列型態。 一般而言，所有堆疊之重佈層形成，位於晶粒以及增層之 鲁上’因此增加料厚度’此與降低晶片尺寸之f求相衝θ突。 因此本發明提出一以堆疊與相鄰排列結構，作為 WLP(板材晶圓）扇出之多晶粒封裝。 【發明内容】 本發明於在其一觀點中，提供 对衷具具有較高 之可罪度以及較低之價格優勢 本發明提供-多晶片封袭結構，其基板 形形成於基板之上表面，以及—通孔結_構= 子線路，於通孔下方連結終端接點 放置(黏著)於容納槽中，-第-介電層形成於第：曰;:： “槽中晶粒與側/ 一重佈導電層（跳)形成於第—介電層之上， 弟 RDL已通孔方式連結，第 ，、中之弟一 層形成於第-跳之上^+ 點。—第一介電 ⑽峨構，时未顯示）Λ^(2含-金屬塾層 Φ a n/ L 第一日日片被放置。一筮二人 電層形成於第二晶片之下 I 弟一介 層陳)形成於此第三導電(二=)’：第二重佈導電 曰之上，其中第—RDL與此第 8 200834876 一晶片接合。一第四介電層形成於第二RDL之下，以霖 接點（其包含一金屬墊層（ubm)結構，圖中未顯示），^ 凸塊形成於第-晶片與第二晶片Μ，以作為結合第一 層之接點與第二介電層之接點。此外，一包覆材料佈滿於 第二晶片四周，可為一選擇性結構設計。 、 第RDL之扇出，由此第一晶片之金屬（紹）塾至终 端墊’經由基板之金屬通孔，並由第一晶粒耦合電氣訊號： 此第二晶粒之上方結構，可以石夕基之晶圓尺寸級封裝 製成’其具有之-增層（第二RDL)與導電凸塊，其製作^ 晶粒切割之前。晶粒切割後，於板材晶圓製程（並與第二
RDL、接點-包含咖結構），使用覆晶黏著方式 此第二晶粒（WLP-CSP)。 I 此夕晶片封裝結構包含 粒 晶 n 人开王少具有兩 、且通孔結構形成導通，其中導線具有終端墊，形 於通孔、、，σ構之下。一第一晶粒與第二晶粒被放置（黏著）於 至少兩^之晶粒容納槽。—第—介電層形成於第—晶粒 =、第二晶粒與其基板間，並且將之填充人槽中^邊 υ壁間隙-第-重佈導電層（RDL)形成於第一導電層 之上’其中此第—祖，藉由通孔結構，與第—晶粒 -晶粒與終端墊接合。一第二介電層形成於第一飢之上 以裸露接點(其包含一金屬墊層⑽M)結 示）〇接著Λ—笛-曰私 墙人 口 r禾顯 接者“二曰曰粒，一弟三介電層形成於第三晶粒之 爲（；主動面上）。一第二重料電層（RDL)形成於第三介電 曰之下，其中其第二RDL接合至第三晶粒，—第四介電層 200834876 形成於第二RDL之下，以為裸露接點（其包含一金屬墊層 (UBM)結構，圖中未顯示）。導電凸塊介於此第一晶粒且/ 或與第二晶粒與第三晶粒間形成，藉由此第一 RDL與第二 RDL接合。 此第三晶粒之上方結構，其可為矽基之晶圓尺寸級封 裝（WLP)製成，其具有其增層（第二RDL)，且其導電凸塊 之製作先於晶粒切割。晶粒切割之後，於已處理之面板上 (具有第一 RDL與接點-包含其金屬墊層UBM結構）以覆晶 ⑩黏著方式黏著此第二晶粒（WLP-CSP)。
I 此第一介電層其包含一彈性介電層。另一實施方式， 此第一與第二介電層包含一矽基介電材料，苯環丁烯BCB 或聚亞醯胺（PI)，其中之矽基介電材料其包含矽氧烷高分 子（SINR)，道康寧（Dow Corning) WL5000系列或其複合 物。其第一與第二介電層可包含一光敏（光圖形轉移 photo-patternable)層。 φ 此基板之材料包含環氧樹脂型之FR5、FR4、BT等 PCB(印刷電路板）、合金、玻璃、石夕、陶瓷或金屬。另一 方式，此基板材料包含合金42(Alloy42)(42%鎳 -58% 鐵）。 本發明進一步提供一方法以形成半導體元件封裝，包 含提供一基板具有一晶粒容納槽形成於一基板之上表面， 且一通孔結構形成導通，其中之導線電路於通孔之下具有 終端接點。接著至少一第一晶粒被重佈，以一取放對位系 統工具，使其具有設計過之線寬。黏性材料至少黏於第一 200834876 * η 曰曰粒之月面，且接著此基材被黏著(於直空肤、 面，且此晶粒位於基板凹mi且·;工狀恶）於晶粒背 著一第-介電層塗佈於第曰Γ具散佈於板上。緊接 曰土饰於弟一晶粒與此基板 此晶粒邊緣與凹槽側壁之間隙。一第 、'真入於 第一介電層上，接著一第-入带@ ^接者形成於此 Q、 弟—介電層被形成於第一 RDT μ =露接點與此UBM結構。一第二且， 介電層被形成於第二晶粒之下(於主動面:：且-“ 跳接著形成於第 ^ 一弟二 •成於*二RDL之下，以形成接觸下緊=二介電層被形 並作為此笛-ρητ 义_孟屬電極（包含UBM製程） 作為此弟一 RDL之保護。導電凸 弟二晶粒間，以作為接合此第一 RDL與二弟二 後-圍阻材料佈滿於第二晶片四取 計。 β 』马廷擇性結構設 圓 於上述製程形成一第二晶粒之方 具有第二晶粒。 3矽基晶 I【實施方式】 類敘:::::較佳之實施例及觀點加以詳細敘述，而此 ., 明專利乾圍。因此，除說明書中之較佳實 外，本發明亦可廣泛實行於其他實施例。 、 且且露一圓尺寸級封裝（WLP)結構，利用一基板 二通孔之電路於其中，且於基板令具一凹 料彳是盍於晶粒與先前之基板上，較佳之光敏 材料為具彈性材料。 ^之光敏 11 200834876 圖一顯示根據本發明之一平板、級封農（panei π a package，PSP)用於系統級封裝（SIP)之剖面視圖，如圖一所 示m級封裝包含-基板2其具有_晶粒容納σ凹槽4 於其中，放置一晶粒18。此基板2可為圓形例如晶圓形狀， 其直徑可為200、300 mm或更大’其亦可為方形形狀/如平 板狀。圖一顯示預先成形基板2之剖面圖，一切割道 為一晶圓尺寸級封裝之切割點或面。如圖所示，此=板^ 形成一凹槽4,且具有電路10，通孔6結構由金屬^注並 中。複數個通孔被建製，由基板上表面至下表面，貫穿基 板2。一導電材料將被重新灌入通孔6以作為電路二二了 終端接點8位於基板之下表面’且藉由導電材料盥通：6 連接。一導電線路丨0被製作於基板2之下表面，一保護層 12例如環氧樹脂錫膏罩幕，形成於導電線路 保護。 乍為 曰晶粒18放置於此基板2之容納凹槽4内，且以黏性（黏 •晶）材料14固定，一般接點（金屬焊墊）形成於晶粒18 2 上。一光敏層或介電層22形成於晶粒18之上， 粒18與凹槽4側壁間之空間。複數個開口以微影製程或曝 光顯影製程，形成於介電層22，此複數個開口各自對準接 觸面通孔6以及晶粒18之接觸或1/〇接點2〇。此重佈層 RDL24S供作為傳導㈣24,其以選擇性移除部分介電^ =、’形成於介電層22之上。其中之跳24作為晶粒二 導通至I/O接點20之電氣連結。藉由於通孔上之接觸導通 面金屬以及於焊墊上之接點金屬’一部份之rdl將在填入 12 200834876 於介電層22之開口。一介電層26形成並覆蓋於RDL 24， 此’1電層26形成於晶粒18、基板2與介電層22之頂上， 複數個開口形成於介電層26中，且與RDL 24曝光部分對
一第二晶片30具有第二接點36,介電材料32被形成 (覆蓋）於一晶片30之表面，以裸露晶片3〇之晶墊36，一 種子金屬層與第二重佈傳導層34,通過介電層32連接至 接點36。此重佈傳導層34為導通連結晶粒3〇之用，其他 介電材料38具有開口被形成（覆蓋）於重佈層34，以裸露重 佈層34接點（錫球接點），以及保護晶粒3〇。此開口之製作 使用傳統方式且對準重佈傳導層34,覆晶球下金屬層 (UBM)形成於接點開口之上，導電（焊接）凸塊4〇接合 24與RDL 34,此結構與終端接點8為栅格陣列封裝 形式之sip(系統級封裝）或SIP-LGA。若是導電凸塊加入， 此為BGA(球柵陣列）之SIP(系統級封裝）或sip_BGA。此處 之表面其具有兩晶片，其為相互面對面。 一保護層42覆蓋於晶片3〇以及導電凸塊之上， 層42之材質可為環氧樹脂、橡膠、樹脂、塑膠或陶曼等。 其須注意，此第-晶片18可經由導電凸塊4(>盘第一。 晶片30、第一 RDL 40與第二RDL 38導通，& = 擇性。由此可見，此第-晶片18置於一⑽4中 ^ 整個SH>高度。此第- RDL配置為一散出形式，以增力^ 間距，致使增加可靠度與散熱性。 ㈢ 衣 此基板2之材料較佳為環氧樹脂型，fr5、 一 一二氮 13 200834876 樹脂（Bismaleimide triazine，ΒΤ)，PCB具有被定義之凹槽 或金屬，合金42具有預先蝕刻之電路。有機基板其具有高 玻璃轉化態溫度為環氧樹脂型，FR5、B —三氮樹脂 (Bismaleimide triazine，BT)形基板其較適用，為其介電材 料烘烤必須不高於基板2之玻璃轉化態溫度，以防止基板 性質改變。其合金42之組成為42%鎳與58%鐵，柯華合 金（Kovar)以可被使用，其組成為29%鎳、17%鈷、54%鐵， 金屬銅亦可使用，而玻璃、陶瓷、矽可作為降低熱膨脹係 籲數之用。 於本發明一實施例中，此介電層22為一彈性介電材質 較佳，其為矽基介電材料，包含矽氧烷高分子（SINR)，道 康寧WL5000系列與其組合物，且其彈性材料可用於釋 放、緩衝熱機械應力。於另一實施例中，此介電層可為聚 亞醯胺（PI)或石夕氧樹脂（silicone resin)，此為一光敏層較 佳，以作為簡化製程。
φ 於本發明另一實施例中，此彈性介電層22為一種CTE 大於100 (ppm/°C)之材料，伸長速率約為40%(30% - 50% 較佳），且其硬度介於塑膠與橡膠間，其中介電層22厚度， 取決於溫度循環測試，RDL/介電層間之應力累積。 於本發明另一實施例中，此RDL 24、34材料包含鈦/ 銅/金之合金或鈦/銅/鎳/金之合金，其RDL 24之厚度由2 微米至15微米，鈦/銅/合金以濺度技術製成，其種子金屬 層亦然，且其銅/金或銅/鎳/金合金由電鍍方式形成，利用 電鍍技術製作RDL，其可使RDL之厚度，於溫度循環中， 14 200834876 足以承受CTE失配。此金屬接點2〇、36可為鋁或銅或其 混合物、。若此F0_WLP結構使用SINR作為彈性介電層與 、銅作為RDL金屬，纟rdL/介電層介面之應力即可被降
參照圖示二，此第一晶片18與此第二晶片3〇被放置 於=納凹槽4巾’於基板2中其具有不同之尺寸，且各自 固疋於一黏著（黏晶）材料14與28。於圖二之上半部，第一 曰曰片18與第二晶片3〇並未設計為堆疊結構，此第二晶片 30位於第—晶片18接鄰’且兩晶片藉由—橫向導通線μ 相互連結’而非藉由通孔結構。如圖所示，此基板至少包 ^兩凹槽’以作為分別容納第一與第、曰曰片。bga封裝之 導電凸塊8a’ LGA封裝之終端接，點8，顯*於圖中。若曰 導電凸塊省略’則其為LGA形式之SIp (系統級封襄）= SIP-LGA。其他之部件類同於圖—，因此其他 被省略。 1 1干 此外，本實施例中之圖三為結合圖一與圖二之觀念， 至少三晶片排列於SIP封裝，其上層晶片％可經由咖 24、34以及導電凸塊4G聯通晶片18，其下層晶片^與 7〇可經由RDL24a接合，且其上層被動元件5〇與6〇心 由RDL 24與下層晶片7〇聯通。 二 其上層晶片30具有增層與焊錫凸塊，先晶粒 (後晶圓製程)’其製程為晶圓級封裝，且其為晶圓級晶: 財封裝（WLP_CSP)結構與製程。此上層晶片％可為倒置 黏著方式，藉由覆晶黏晶機將之置於下層晶片（板狀晶圓） 15 200834876 腎 之上、，藉由表面黏著技術（SMT)製程之紅外線迴焊焊接， 且其被動το件50與60可與下層晶片一並黏著。 ㈣42形成附帶於此第二晶片％，此被動元件 〇以及v電凸塊40為選擇性結構，其保護層42之 料可為可為環氧樹脂、橡膠、樹脂、㈣或m 如圖1 - 3所示，此晶粒扇出RDLs 24、池 ，結構，其向下聯通至終端接點8。此其不同於習：之 =曰粒封裝⑽p)㈣，其堆疊晶粒各層，致使增加封襄 =H其違反晶粒封裝厚度之法則。相反地，本案 ;!= 點位於晶粒嬋墊側之另-面。其聯通線路藉由通 厚===，至'^接點8’因此其晶粒封裝 有放之縮減，本發明之封裝將薄於習知技術。進— 其f板於封裝前預先備置，此凹槽4與導線電路1〇 乳疋予 =決定’因此其產能將比先前提升。本發明揭露之 WLP扇出，亦無堆疊增層於RDL上。 ;曰曰圓製輊後且將其背面研磨至所欲之厚度，其曰 :割成晶粒。其基板預先形成内建線路於其中，且^星 凹h。其基板材料為具有較高玻璃轉化態溫度巧性併 = =5/BT印刷電路板較佳’其基板可具有不同面積之二 ( 等於晶粒面積加各側邊約1〇〇微米），以容納不 2尺寸之晶粒，且其凹槽深度大於晶粒厚度約20至3〇 n 容納黏晶材料厚度。其内部連結接點可被重佈， 較適之面積放寬線寬尺寸，增加產出良率。 本發明所述之製程其包含對準工具（板），於其上具有 16 200834876 =案:,者备水圖案塗佈於工具上(作為黏著晶粒表 面），接者使用精密取放對位系統，以覆晶方式將已知良裸 晶粒（known g00d dies)以期望之間距置於工且 圖案將晶片黏於工具上，緊接，、钻膠 北 冢骚者日日粒黏耆材料塗佈於晶粒 月面’其基板上表面除了凹槽外亦圖佈黏膠圖冑 空固化其晶粒黏著材料，接著由呈一 立R |丄 八…板材日日Η (板材晶圓
粒被黏著於基板之凹槽内）將其分開。晶粒黏著材 料以熱烘烤確保其晶粒固著於基板上。 另一方式，黏晶機以精密對位方式，且晶粒黏著材料 下基:曰了内，亦即上層之覆晶晶片已放置於板材 曰曰51上（下層曰曰片具有增層）’接著迴焊爐焊接覆晶盘/或彭 程中置於板材晶圓之被動元件，其上層晶片（粒）於製程後 具有一覆晶凸塊結構（WLP-CSP)。 因為晶粒已於基板上重佈，接著執行一清潔製程，以 乾式與/或濕式清潔製程，清潔晶粒表面。下一步，為塗佈 介電材料於板材表面，接著藉由真空程序 氣：殘 存於板材上。緊接著實施微影製㈣露出接觸面與金屬= 焊墊與/或切割道，接著施行電漿清潔製程，以清潔接觸面 與金屬⑻焊墊。下一步驟為以濺鑛鈦/銅作為金屬屬種 子，並接著塗佈光阻时電層與金屬層種子上，以形成重 佈層（RDL)圖案。接著施行電鍍製程以形成銅/金或銅/錄/ 金作為重佈層金屬’接著移去光阻並乾姓刻金屬層以及露 出接觸金屬墊’以形成RDL金屬走線。緊接著，其下一步 為披覆或塗佈上介電層以及露出焊料圖塊之金屬塾與/或 17 200834876 ψ 切割道’此即完成其第一層板材製程。 後續程序可重複上述之步驟，以形成多層金屬與介電 層，以完成第二層晶粒。濺鍍鈦/銅步驟以形成金屬種子 層，且塗佈PR以形成RDL圖案，接著電鑛步驟以形成銅 /金於RDL圖案，接著剝除pr且以濕蝕刻種子金屬，以形 成第二重佈重佈金屬走線，一上介電層型成以保護其第二 RDL走線。 越薄之晶粒（約5〇 - 127微米），可得較佳製程特性 與可靠性，其製程進一步包含藉由覆晶黏晶機黏著上層晶 片（CSP)。之後其上層晶片（CSP)被黏著，以熱迴焊製程作 焊接，接著導電（焊接）凸塊（球）連結於第一 RDL與第二 RDL。 ' 接著執行測試，以垂直測試卡作板材晶圓級最後測 試。經測試後，其基板被切割為單一封裝，成為具有多晶 粒之單獨SIP單元，此封裝為分開地包裝，經取放封裝（元 馨件)至托盤、膠帶或捲帶。 本發明所述具有之優點： 其剷製備基板具有預先成型之凹槽；其凹槽大約等於 晶粒大小加上兩侧邊各50至100微米裕度，此可以填充彈 性介電材料，以吸收矽晶粒與基板間（FR5/BT) CTE差異所 產生之熱機械應力，作為應力緩衝釋放區域。肇因於於晶 粒與基板上表面簡單增層，此Slp封裝之產能將被增加（生 產時間減少）。其導線電路與終端接點於晶粒之主動面之另 一側，其晶粒放置程序與現今同。本發明之製程無須填入 18 200834876 t 砂心黏糊（樹脂、環氧化合物、[聚]矽氧橡膠等），亦無焊料 與母板PCB造成CTE差異。其晶粒與基板刚深度差異 約為20微米至30微米（作為晶粒黏著材料裕度），晶粒黏 著於基板之凹槽後，其晶粒與基板表面基準相同，以利辦 層程序。只有切基介電材料⑻舰較佳）塗佈於主動面^ 基板（FR45或BT較佳）表面，其接觸面結構以光罩製程露 出，只有當介電材料（SINR)為光敏材料作為接 真空製程用於SINR塗佈時減少衰令田妾 眷 土饰时减）乳泡因素。於晶粒連結於 基板前，其晶粒黏著材料先塗佈於晶粒背面。本發明於封 該與基板級之可靠度皆優妹昔，尤其於板級之溫度循 忒’其歸因於基板與PCB母板之cte相同，因此益 熱機械應力產生至焊料凸塊/球極。其成本低且製程簡單： 亦於製作結封裝（多晶粒封裝） 衣粒間早 =已詳述本發明之較佳實施例，在不背離本發明之 精=㈣的前提下，關於本發明多種的改變與取代是可 # =本發明只受下㈣請__料效範相 【圖式簡單說明】 圖。圖-顯示根據本發明之堆疊SIP之扇出結構之剖面視 心圖—顯不根據本發明之平行（並排）SIP之扇出έ士蠢 剖面視圖。 屬出結構之 圖三顯示根據本 面視圖。 發明之另一堆疊SIP之扇出結構之剖 19 200834876 要 元件符號說明】 2 基板 24a 重 佈傳導層 4 容納凹槽 26 介 電層 6 通孔 28a 切 割道 8 終端接點 30 第 二晶片 8a 導電凸塊 32 介 電層 10 導電線路 34 第 二重佈傳導層 12 保護層 36 第 二接點 14 黏性（黏晶）材料 40 導 電（焊接）凸塊 18 晶粒 42 保 護層 20 接點 50 上 層被動元件 22 介電層 60 上 層被動元件 24 重佈傳導層 70 下 層晶片 20

Claims (1)

  1. 200834876 十、申請專利範圍： 1 · 一多晶粒封裝結構其包含： 一基板其具有一晶粒容納凹槽形成於此基板之上表面 且一通孔結構貫通形成，其中具一導線電路具終端接點 形成於此通孔結構之下； … 一第一晶粒放置於此晶粒容納凹槽内； 一第一介電層形成於此第一晶粒與此基板之上； 鲁 一第一重佈傳導層（RDL)形成於此第一介電層之上，其 中第一 RDL藉由此通孔結構接合此第一晶粒與此終端 接點； > 一第二介電層形成於此第一 RDL之上； 一苐^一晶粒 一第三介電層形成於此第二晶粒之下； 一第二重佈傳導層（RDL)形成於此第三介電層之下，於 此第二重佈傳導層RDL接合此第二晶粒； • 一第四介電層形成於此第二重佈傳導層RDL之下； 導電凸塊形成於第一晶粒與第二晶粒間，以接合此第一 重佈傳導層RDL與此第二重佈傳導層RDL。 2·如申請專利範圍第1項所提出之結構，其中此第一介電 層包含一彈性介電層。 3·如申請專利範圍第1項所提出之結構，其中此第一與此 第二介電層包含一矽基介電材料，苯環丁烯（BCB)或聚 21 200834876 亞醯胺（pi)其中包含一矽 (SINR)，如道康寧 WL5000 基介電材料矽氧烷高分子 系列或其混成物。 4.如申請專利範圍第1項所提出之結構，其中之此第-介 電層與此第二介電層包含—光敏（光圖案化）層。
    5·如申請專利範圍第 一 RDL·組成為一 銅/鎳/金合金。 1項所提出之結構，其中此第一或第 合金，其可包含鈦/銅/金之合金或鈦/ 6·如申請專利範圍第1項所提出之結構，其中此第一 rdl 之扇出，自此第一晶粒而出。 請專利範圍第β所提出之結構，其中此基材之材 =包含環氧樹脂0R5、FR4、BT、pCB_f_)、 口金、玻璃、矽、陶瓷或金屬等。 8.如申請專利範圍第1JM所提出之結構，進一步包含 阻材料形成於此第二晶粒之周圍。 9· 一多晶粒封裝其包含： 基^其至少具有兩晶粒容納凹槽形成於此基板上表 ^以谷納至少兩晶粒且通孔結構形成於其間貫通，其 V線電路具有終端接點形成於此通孔結構之下；/、 22 200834876 一第一晶粒與第二晶粒放置於此分開之至少兩晶粒容 納凹槽； 一第一介電層形成於此第一晶粒，第二晶粒與此基板之 上，一第一重佈導電層RDL形成於此第一介電層之上， 其中此第一 RDL藉由此通孔結構為接合此第—晶粒、 第二晶粒與終端接點； 一弟二介電層形成於此第一 RDL之上； 一第三晶粒； 鲁 一第三介電層形成於此第三晶粒之下； 一第二重佈導電層（RDL)形成於此第三介電層之下，其 中此第二RDL接合此第三晶粒； ’、 一第四介電層形成於此第二RDL之下； 粒以接合此第 導電凸塊形成於此第一晶粒與此第三 一 RDL 與第二 rdL。 ，其中其中此第一 ❿10·如申請專利範圍第9項所提出之結構 介電層包含一彈性介電層。 ，其中此第一與此 (SINR)，
    11·如申請專利範圍第9項所提出之結構 第二介電 亞醯胺（I 之結構，其中之此第一介 12.如申請專利範圍第9項所提出 23 200834876 電層與此第二介電層包含一光敏（光圖案化）層。 13·如申請專利範圍第9項所提出之結構，其中此第一腿 、、、成為s 1，其可包含鈦/銅/金之合金或鈦/銅/鎳/金 合金。 14.如申請專利範圍第9項所提出之結構，其中此第一狐 之扇出，自此第一晶粒而出。 I申，專利範圍第9項所提出之結構，其中此第-晶粒 /、此弟二晶粒藉由此第一 RDL相互聯通。 m專利範圍第9項所提出之結構，其中此基材之材 二a氧樹脂型FR5、FR4、BT、PCB(印刷電路板）、 口至、玻璃、矽、陶瓷或金屬等。 RDL /銅/金之合金或鈦/銅/鎳/金 17:申請專利範圍第9項所提出之結構，其中此第 、、且成為一合金，其可包含鈦 合金。 18. :申請專利範圍第9項所提出之結構，進一步包含至少 —破動元件黏著並連接於此第一 RDL之接點。 19. 如申請專利範圍第1項所提出之結構，進一步包含一圍 24 200834876 阻材料形成於此第三晶粒之周圍。 2〇· —形成半導體元間封裝之方法其包含： 提供一基板其具有晶粒容納凹槽形成於此基板之上表 面，且一通孔結構形成貫通其中，於此通孔之下，其中 具有終端接點之導線電路； 於工具上至少重佈-第—晶粒，藉由精密取放對位系統 使具有所欲之線寬；
    塗佈黏著材料至少於此第面， 黏著此基板至此晶粒背面，且此晶粒放置於此基板之此 凹槽上，且藉由此工具分開形成板材晶圓； 塗佈帛-介電層至少於此第—晶粒與此基板，並且將 之填充入此凹槽中晶粒邊緣與側壁間隙； 死^成弟一 RDL於此第一介電層之上· 以作為露出接 ，以作為保護此 晶粒之間，以連 rDL之第二接 形成一第二介電層於此第一 RDL之上 觸點； 施行一第二晶粒； 形成一第三介電層於此第二晶粒之下； 形成一第二RDL於此第三介電層之下· 形成一第四介電層於此第二RDL之下 第二RDL並露出第二第二接點；且 形成一導電凸塊於此第一晶粒與此第二 接此第一 RDL之此第一接點與此第二 fi 〇 25 200834876 21.:::請:=圍第20項所提出之方法，其中此第-與 ^二電層包含4基介電材料，苯環丁 m·、 i 基介電材料石夕氧院高分子 )’如道康寧WL5_系列或其混成物。
    22.如申請專利範圍第2G項所提出之結構，其中之 介電層與此第二介電層包含-光敏(光圖案化)層 23·如申請專利範圍第 苐一 RDL組成為一 /銅/鎳/金合金。 20項所提出之結構，其中此第一或 合金，其可包含鈦/銅/金之合金或鈦 24. 如申請專利範圍第2〇項所提出之方法，其中此基材之 材料包含環氧樹㈣FR5、FR4、BT、pCB(印刷電路 板）、合金、玻璃、矽、陶瓷或金屬等。 25. 如申請專利範圍第20項所提出之方法，進一步包含_ 圍阻材料形成於此第二晶粒之周圍。 26·如申睛專利範圍f 20項所提出之方法，其中此第 * 1 曰曰 通晶圓尺寸級封裝製成（WLP)並具有增層（RDL)，且 焊料凸塊/球極於晶粒之上方表面，接著利用覆晶黏著 方式黏著此第二晶粒（WLP_CSP)於基材晶圓製程上，以 26 200834876 回焊焊料凸塊/球極以接合此第一 RDL之第一接點以及 此第二RDL之第二接點。
    27
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