CN110828496B - 半导体器件及其制造方法 - Google Patents
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Abstract
本发明提供一种半导体器件及其制造方法,其中,所述半导体器件制造方法包括如下步骤:S1、在硅基片的正面开设需求数量的槽体;S2、将第一芯片、第二芯片的晶圆减薄到需求厚度;S3、将第一芯片、第二芯片分别固定于开设的槽体中;S4、在第一芯片、第二芯片表层的阻焊层上设置焊点;S5、将硅基片的背面进行减薄,再第三芯片以倒装方式焊接于设置的焊点上。本发明的半导体器件制造方法中,将第一芯片和第二芯片通过硅基片进行封装,并通过倒装方式实现第三芯片与第一芯片和第二芯片之间互连,最终封装厚度小于600um,实现了超薄、更小体积的封装,且实现三维互连,信号传输距离更远、更快。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种半导体器件及其制造方法。
背景技术
图像传感器是利用光电器件的光电转换功能。将感光面上的光像转换为与光像成相应比例关系的电信号。与光敏二极管,光敏三极管等“点”光源的光敏元件相比,图像传感器是将其受光面上的光像,分成许多小单元,将其转换成可用的电信号的一种功能器件。
与图像传感技术相关的芯片包括:CMOS芯片、ISP芯片和DDR芯片。目前,图像传感器封装是将CMOS芯片,ISP芯片和DDR芯片平放在PCB 板上。然而,上述封装方式中通过打线方式将信号引出,该传统的图像传感器的封装方式存在封装体积大且封装厚度厚的问题。因此,针对如上述问题,有必要提出进一步的解决方案。
发明内容
本发明旨在提供一种半导体器件及其制造方法,以克服现有技术中存在的不足。
为解决上述技术问题,本发明的技术方案是:
一种半导体器件制造方法,其包括如下步骤:
S1、在硅基片的正面开设需求数量的槽体;
S2、将第一芯片、第二芯片的晶圆减薄到需求厚度;
S3、将第一芯片、第二芯片分别固定于开设的槽体中;
S4、在第一芯片、第二芯片表层的阻焊层上设置焊点;
S5、将硅基片的背面进行减薄,再第三芯片以倒装方式焊接于设置的焊点上。
作为本发明的半导体器件制造方法的制造方法,所述步骤S2具体包括:先将第一芯片、第二芯片的晶圆减薄到需求厚度,再将减薄后的晶圆切割形成单颗芯片。
作为本发明的半导体器件制造方法的制造方法,所述步骤S2具体包括:先切割形成单颗芯片,再对单颗第一芯片、第二芯片的晶圆减薄到需求厚度。
作为本发明的半导体器件制造方法的制造方法,所述步骤S3中,将第一芯片、第二芯片通过粘胶方式粘接于所在槽体的底面。
作为本发明的半导体器件制造方法的制造方法,所述步骤S3中,在所述第一芯片、第二芯片的表面及第一芯片、第二芯片与槽体之间的间隙形成钝化层,同时在钝化层上形成芯片的焊接位置。
作为本发明的半导体器件制造方法的制造方法,所述步骤S3和S4之间,还包括:通过重布线的方式,将第一芯片和第二芯片的信号引出。
作为本发明的半导体器件制造方法的制造方法,所述重布线的方式为金属重布线,其包括:在第一芯片和第二芯片的焊接位置沉积一层种子层,再光刻出线路,然后将金属线路加厚至要求的厚度。
作为本发明的半导体器件制造方法的制造方法,所述重布线的方式为多层金属重布线,其包括:在第一芯片和第二芯片的焊接位置逐层沉积种子层,在沉积的同时光刻出线路,在最后一层线路上采用化镀方式形成保护层。
作为本发明的半导体器件制造方法的制造方法,所述半导体器件制造方法还包括:
S6、将步骤S5得到的产品切割,得到单颗封装体,将所述单颗封装体通过打线方式焊接到PCB板上。
作为本发明的半导体器件制造方法的制造方法,所述第一芯片为ISP芯片,所述第二芯片为DDR芯片,所述第三芯片为CMOS芯片。
为解决上述技术问题,本发明的技术方案是:
一种半导体器件,其通过如上所述半导体器件制造方法得到的,所述半导体器件的总体封装厚度小于600um。
与现有技术相比,本发明的有益效果是:本发明的半导体器件制造方法中,将第一芯片和第二芯片通过硅基片进行封装,并通过倒装方式实现第三芯片与第一芯片和第二芯片之间互连,最终封装厚度小于600um,实现了超薄、更小体积的封装,且实现三维互连,信号传输距离更远、更快。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明中记载的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1-4为本发明的半导体器件制造方法的工艺原理图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明的半导体器件制造方法可适用于具有三个以上芯片的半导体器件的封装。例如,可适用于图像传感器的超薄封装。其中,所述图像传感器包括:CMOS芯片、ISP芯片和DDR芯片,通过本发明的半导体器件制造方法,实现了超薄、更小体积的封装,且实现三维互连,信号传输距离更远、更快。
本发明的半导体器件制造方法包括如下步骤:
S1、在硅基片的正面开设需求数量的槽体;
S2、将第一芯片、第二芯片的晶圆减薄到需求厚度;
S3、将第一芯片、第二芯片分别固定于开设的槽体中;
S4、在第一芯片、第二芯片表层的阻焊层上设置焊点;
S5、将硅基片的背面进行减薄,再第三芯片以倒装方式焊接于设置的焊点上。
针对上述步骤,结合图像传感器的实施例,对该图像传感器的封装的技术方案进行如下举例说明。
如图1所示,针对步骤S1。
在硅基片1的正面通过刻蚀方式刻出槽体11,槽深可依据封装要求,蚀刻出不同的深度。槽体11个数由埋入的ISP芯片和DDR芯片的数量决定。
如图2所示,针对步骤S2。
将ISP芯片2、DDR芯片3的晶圆减薄到需求厚度,具体可采用如下两种并列的实施方式。
一个实施方式中,先将ISP芯片2、DDR芯片3的晶圆减薄到需求厚度,再将减薄后的晶圆切割形成单颗芯片。另一个实施方式中,先切割形成单颗芯片,再对单颗ISP芯片2、DDR芯片3的晶圆减薄到需求厚度。通过上述减薄、切割的处理方式,有利于实现最终封装厚度小于600um。
针对步骤S3。
将ISP芯片2、DDR芯片3通过粘胶方式粘接于所在槽体11的底面。例如,可通过DAF膜或者印胶的方式实现上述粘接的目的。
所述步骤S3还包括:在所述ISP芯片2、DDR芯片3的表面及ISP芯片 2、DDR芯片3与槽体11之间的间隙形成钝化层4,同时在钝化层4上形成芯片的焊接位置。例如,通过真空压膜的方式在芯片表面形成钝化层4,同时将芯片与槽体11的缝隙填充,通过曝光、显影将芯片的焊接位置打开。
此外,所述步骤S3和S4之间,还包括:通过重布线的方式,将ISP芯片2和DDR芯片3的信号引出。
一个实施方式中,所述重布线的方式为金属重布线,其包括:在ISP芯片2和DDR芯片3的焊接位置沉积一层种子层5,如Ti/Cu、Al等,再光刻出线路,然后将金属线路加厚至要求的厚度。
另一个实施方式中,对于I/O接口高密集产品,可采用多层布线方式。此时,所述重布线的方式为多层金属重布线,其包括:在ISP芯片2和DDR芯片3的焊接位置逐层沉积种子层5,在沉积的同时光刻出线路,在最后一层线路上采用化镀方式形成保护层,以防止金属线路的腐蚀。
针对步骤S4。在芯片表层形成阻焊层6的目的在于防止水汽进入。
如图3所示,针对步骤S5。将CMOS芯片7以倒装方式焊接于设置的焊点上时,用超薄玻璃100-200um进行键合,通过TSV技术实现超薄封装,总体封装厚度小于600um。
如图4所示,所述半导体器件制造方法还包括:
S6、将步骤S5得到的产品切割,得到单颗封装体,将所述单颗封装体通过打线方式焊接到PCB板8上。
基于如上所述的半导体器件制造方法,本发明还提供一种半导体器件。
此时,所述半导体器件通过如上所述半导体器件制造方法得到的,所述半导体器件的总体封装厚度小于600um。当所述第一芯片为ISP芯片,所述第二芯片为DDR芯片,所述第三芯片为CMOS芯片,所述半导体器件为图像传感器。
综上所述,本发明的半导体器件制造方法中,将第一芯片和第二芯片通过硅基片进行封装,并通过倒装方式实现第三芯片与第一芯片和第二芯片之间互连,最终封装厚度小于600um,实现了超薄、更小体积的封装,且实现三维互连,信号传输距离更远、更快。
对于本领域技术人员而言,显然本发明不限于上述示范性实施例的细节,而且在不背离本发明的精神或基本特征的情况下,能够以其他的具体形式实现本发明。因此,无论从哪一点来看,均应将实施例看作是示范性的,而且是非限制性的,本发明的范围由所附权利要求而不是上述说明限定,因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外,应当理解,虽然本说明书按照实施方式加以描述,但并非每个实施方式仅包含一个独立的技术方案,说明书的这种叙述方式仅仅是为清楚起见,本领域技术人员应当将说明书作为一个整体,各实施例中的技术方案也可以经适当组合,形成本领域技术人员可以理解的其他实施方式。
Claims (9)
1.一种半导体器件制造方法,其特征在于,所述半导体器件制造方法包括如下步骤:
S1、在硅基片的正面开设需求数量的槽体;
S2、将第一芯片、第二芯片的晶圆减薄到需求厚度;
所述步骤S2具体包括:先将第一芯片、第二芯片的晶圆减薄到需求厚度,再将减薄后的晶圆切割形成单颗芯片;或者;所述步骤S2具体包括:先切割形成单颗芯片,再对单颗第一芯片、第二芯片的晶圆减薄到需求厚度;
S3、将第一芯片、第二芯片分别固定于开设的槽体中;
S4、在第一芯片、第二芯片表层的阻焊层上设置焊点;
S5、将硅基片的背面进行减薄,再第三芯片以倒装方式焊接于设置的焊点上;
所述第一芯片为ISP芯片,所述第二芯片为DDR芯片,所述第三芯片为CMOS芯片;所述DDR芯片分置于所述ISP芯片的两侧;且将CMOS芯片以倒装方式焊接于设置的焊点上时,用超薄玻璃100-200um进行键合,通过TSV技术实现超薄封装,总体封装厚度小于600um。
2.根据权利要求1所述的半导体器件制造方法,其特征在于,所述步骤S3中,将第一芯片、第二芯片通过粘胶方式粘接于所在槽体的底面。
3.根据权利要求1或2所述的半导体器件制造方法,其特征在于,所述步骤S3中,在所述第一芯片、第二芯片的表面及第一芯片、第二芯片与槽体之间的间隙形成钝化层,同时在钝化层上形成芯片的焊接位置。
4.根据权利要求1或2所述的半导体器件制造方法,其特征在于,所述步骤S3和S4之间,还包括:通过重布线的方式,将第一芯片和第二芯片的信号引出。
5.根据权利要求4所述的半导体器件制造方法,其特征在于,所述重布线的方式为金属重布线,其包括:在第一芯片和第二芯片的焊接位置沉积一层种子层,再光刻出线路,然后将金属线路加厚至要求的厚度。
6.根据权利要求4所述的半导体器件制造方法,其特征在于,所述重布线的方式为多层金属重布线,其包括:在第一芯片和第二芯片的焊接位置逐层沉积种子层,在沉积的同时光刻出线路,在最后一层线路上采用化镀方式形成保护层。
7.根据权利要求1所述的半导体器件制造方法,其特征在于,所述半导体器件制造方法还包括:
S6、将步骤S5得到的产品切割,得到单颗封装体,将所述单颗封装体通过打线方式焊接到PCB板上。
8.根据权利要求1所述的半导体器件制造方法,其特征在于,所述第一芯片为ISP芯片,所述第二芯片为DDR芯片,所述第三芯片为CMOS芯片。
9.一种半导体器件,其特征在于,所述半导体器件通过如权利要求1至8任一项所述半导体器件制造方法得到的,所述半导体器件的总体封装厚度小于600um。
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