KR970029088A - Device for transferring data of main processor - Google Patents

Device for transferring data of main processor Download PDF

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Publication number
KR970029088A
KR970029088A KR1019950042990A KR19950042990A KR970029088A KR 970029088 A KR970029088 A KR 970029088A KR 1019950042990 A KR1019950042990 A KR 1019950042990A KR 19950042990 A KR19950042990 A KR 19950042990A KR 970029088 A KR970029088 A KR 970029088A
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KR
South Korea
Prior art keywords
data
timing synchronization
out memory
transmission
signal
Prior art date
Application number
KR1019950042990A
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Korean (ko)
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KR100238150B1 (en
Inventor
이영준
Original Assignee
김광호
삼성전자 주식회사
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Priority to KR1019950042990A priority Critical patent/KR100238150B1/en
Publication of KR970029088A publication Critical patent/KR970029088A/en
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Publication of KR100238150B1 publication Critical patent/KR100238150B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

1. 청구범위에 기재된 발명이 속한 기술분야1. TECHNICAL FIELD OF THE INVENTION

메인프로세서의 데이타를 전송하는 장치에 관한 것이다.It relates to a device for transmitting data of the main processor.

2. 발명이 해결하려고 하는 기술적 과제2. The technical problem to be solved by the invention

메인프로세서가 데이타를 전송하고자 할 대 데이타처리기로부터 상태 신호가 발생하였는지 아닌지를 매번 체크함에 따라 발생하는 타이밍상의 손실을 줄여 시스템의 성능이 저하됨을 방지한다.Each time the main processor attempts to transfer data, it checks whether or not a status signal has been generated from the data processor, thereby reducing the timing loss caused by the system.

3. 발명의 해결방법의 요지3. Summary of Solution to Invention

본 발명에 따른 데이타 전송장치는 외부로부터 입력되는 데이타를 저장하기 위한 선입선출메모리를 적어도 포함하고 있으며, 타이밍동기를 위한 신호를 주기적으로 발생하는 데이타처리수단과; 상기 선입선출메모리에 미리 설정된 양만큼의 데이타가 라이트된 경우 상기 타이밍동기신호를 소정 시간 지연시켜 출력하고, 상기 선입선출메모리에 상기 설정된 양만큼의 데이타가 라이트되어 있지 않은 경우에는 상기 타이밍동기신호를 직접 출력하는 신호처리수단과; 전송을 위한 데이타를 상기 신호처리수단으로부터 출력되는 타이밍동기신호에 따라 동기시켜 상기 데이타처리수단에 출력함으로써 상기 전송을 위한 데이타가 상기 선입선출메모리에 라이트되도록 하는 전송데이타 공급수단으로 구성한다.A data transmission apparatus according to the present invention includes at least a first-in first-out memory for storing data input from the outside, and includes data processing means for periodically generating a signal for timing synchronization; The timing synchronization signal is output by delaying the timing synchronization signal for a predetermined time when the predetermined amount of data is written to the first-in-first-out memory, and the timing synchronization signal is output when the data for the set amount is not written in the first-in-first-out memory. Signal processing means for directly outputting; And transmission data supply means for synchronizing the data for transmission in accordance with the timing synchronization signal output from the signal processing means and outputting the data for transmission to the first-in first-out memory.

4. 발명의 중요한 용도4. Important uses of the invention

주문형 비디오의 데이타 전송장치.Data transmission device for video on demand.

Description

메인프로세서의 데이타를 전송하기 위한 장치Device for transferring data of main processor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음As this is a public information case, the full text was not included.

제2도는 본 발명에 따른 데이타 전송장치에 대한 블럭구성도,2 is a block diagram of a data transmission apparatus according to the present invention;

제3도는 제2도에서 신호처리부의 구성을 상세하게 나타내는 도면,3 is a view showing in detail the configuration of the signal processing unit in FIG.

제4도는 본 발명에 따른 데이타 전송장치에 대한 동작파형도.4 is an operating waveform diagram of a data transmission apparatus according to the present invention.

Claims (4)

데이타 전송장치에 있어서; 외부로부터 입력되는 데이타를 저장하기 위한 선입선출메모리를 적어도 포함하고 있으며, 타이밍동기를 위한 신호를 주기적으로 발생하는 데이타처리수단과; 상기 선입선출메모리에 미리 설정된 양만큼의 데이타가 라이트된 경우 상기 타이밍동기신호를 소정 시간 지연시켜 출력하고, 상기 선입선출메모리에 상기 설정된 양만큼의 데이타가 라이트되어 있지 않은 경우에는 상기 타이밍동기신호를 직접 출력하는 신호처리수단과; 전송을 위한 데이타를 상기 신호처리수단으로부터 출력되는 타이밍동기신호에 따라 동기시켜 상기 데이타처리수단에 출력함으로써 상기 전송을 위한 데이타가 상기 선입선출메모리에 라이트되도록 하는 전송데이타 공급수단으로 구성함을 특징으로 하는 장치.A data transmission apparatus; At least a first-in, first-out memory for storing data input from the outside, the data processing means for periodically generating a signal for timing synchronization; The timing synchronization signal is output by delaying the timing synchronization signal for a predetermined time when the predetermined amount of data is written to the first-in-first-out memory, and the timing synchronization signal is output when the data for the set amount is not written in the first-in-first-out memory. Signal processing means for directly outputting; And transmission data supply means for synchronizing the transmission data with the timing synchronization signal output from the signal processing means and outputting the data for transmission to the first-in first-out memory. Device. 제1항에 있어서, 상기 전송데이타 공급수단은 상기 데이타처리수단의 데이타처리속도와 상이한 데이타 처리속도를 가지는 중앙처리장치임을 특징으로 하는 장치.The apparatus according to claim 1, wherein said transmission data supply means is a central processing unit having a data processing speed different from that of said data processing means. 데이타 전송장치에 있어서 : 램과, 소정 데이타를 저장하기 위한 선입선출메모리를 적어도 포함하고 있으며, 상기 선입선출메모리에 라이트되어 있는 데이타를 리드하여 상기 램에 저장시키고, 상기 선입선출메모리에 미리 설정된 양만큼의 데이타가 라이트된 경우 이를 나타내는 상태신호를 발생하고, 타이밍동기신호를 주기적으로 발생하는 데이타처리수단과; 상기 상태신호가 발생되는 경우 상기 상태신호의 발생이 차단될 때까지 상기 타이밍동기신호를 지연시켜 출력하는 신호처리수단과; 상기 지연된 타이밍동기신호에 전소을 위한 데이타를 동기시켜 상기 데이타처리수단으로 출력함으로써 상기 전송을 위한 데이타가 상기 선입선출메모리에 라이트되도록 하는 전송데이타 공급수단으로 구성함을 특징으로 하는 장치.A data transfer apparatus, comprising: a RAM and at least a first-in first-out memory for storing predetermined data, wherein the data written to the first-in first-out memory is read and stored in the RAM, and the preset amount is set in the first-in first-out memory. Data processing means for generating a state signal indicative of this data and writing a timing synchronization signal periodically; Signal processing means for delaying and outputting the timing synchronization signal until generation of the state signal is interrupted when the state signal is generated; And transmission data supply means for synchronizing data for powering off with the delayed timing synchronization signal and outputting the data to the data processing means so that the data for transmission is written to the first-in first-out memory. 제3항에 있어서, 상기 전송데이타 공급수단은 상기 데이타처리수단의 데이타처리속도와 상이한 데이타 처리속도를 가지는 중앙처리장치임을 특징으로 하는 장치.4. The apparatus according to claim 3, wherein the transmission data supply means is a central processing unit having a data processing speed different from that of the data processing means. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950042990A 1995-11-22 1995-11-22 Apparatus for transferring data of main processor KR100238150B1 (en)

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Application Number Priority Date Filing Date Title
KR1019950042990A KR100238150B1 (en) 1995-11-22 1995-11-22 Apparatus for transferring data of main processor

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Application Number Priority Date Filing Date Title
KR1019950042990A KR100238150B1 (en) 1995-11-22 1995-11-22 Apparatus for transferring data of main processor

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KR970029088A true KR970029088A (en) 1997-06-26
KR100238150B1 KR100238150B1 (en) 2000-01-15

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