KR960029992A - Data transmission device - Google Patents

Data transmission device Download PDF

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Publication number
KR960029992A
KR960029992A KR1019950000855A KR19950000855A KR960029992A KR 960029992 A KR960029992 A KR 960029992A KR 1019950000855 A KR1019950000855 A KR 1019950000855A KR 19950000855 A KR19950000855 A KR 19950000855A KR 960029992 A KR960029992 A KR 960029992A
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KR
South Korea
Prior art keywords
data
counter
memory
transmission
latch
Prior art date
Application number
KR1019950000855A
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Korean (ko)
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KR100316310B1 (en
Inventor
이득영
Original Assignee
김광호
삼성전자 주식회사
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Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019950000855A priority Critical patent/KR100316310B1/en
Publication of KR960029992A publication Critical patent/KR960029992A/en
Application granted granted Critical
Publication of KR100316310B1 publication Critical patent/KR100316310B1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)

Abstract

어드레스버스를 개지하지 않고 메모리간에 데이타를 전송하는 데이타전송장치가 개시된다.A data transfer apparatus for transferring data between memories without interposing an address bus is disclosed.

본 발명에 따른 데이타전송장치는 리세트단자에 제공되는 데이타유효신호에 응답하여 활성화되어 클럭단자에 제공되는 전송클럭신호를 계수하고, 계수값을 제1메모리의 독출어드레스로 제공하는 제1카운터; 클럭단자에 제공되는 전송클럭신호에 응답하여 제1메모리에서 독출된 데이타를 래치하는 제1래치; 제1래치와 제2메모리 사이에 설치되어, 제1래치에 의해 래치된 데이타를 제2메모리에 제공하는 데이타버스; 리세트단자에 제공되는 데이타유효신호에 응답하여 활성화되어 클럭잔자에 제공되는 전송클럭신호를 계수하고, 계수값을 제2메모리의 기입어드레스로 제공하는 제2카운터; 데이타의 전송개시 및 종료를 나타내는 데이타유효신호를 발생하여 제1카운터와 제2카운터의 리세트단자에 제공하고, 데이타전송을 지시하는 전송클럭신호를 발생하여 제1카운터 및 제2카운터의 클럭단자와 제1래치의 클럭단자에 제공하는 제어를 포함함을 특징으로 한다.A data transmission apparatus according to the present invention comprises: a first counter activated in response to a data valid signal provided to a reset terminal to count a transmission clock signal provided to a clock terminal and providing a count value to a read address of a first memory; A first latch for latching data read from the first memory in response to a transmission clock signal provided to a clock terminal; A data bus provided between the first latch and the second memory to provide data latched by the first latch to the second memory; A second counter that is activated in response to the data valid signal provided to the reset terminal to count the transmission clock signal provided to the clock residue and provides the count value to the write address of the second memory; Generates a data valid signal indicating the start and end of data transfer and provides it to the reset terminals of the first counter and the second counter, and generates a transmission clock signal instructing data transfer to generate the clock terminal of the first counter and the second counter. And control provided to the clock terminal of the first latch.

본 발명에 따른 데이타전송장치는 전송클럭신호에 동기시켜 송신측과 수신측의 어드레스를 발생시키도록 함으로써 어드레스버스를 개재하지 않고도 데이타를 전송할 수 있으므로 전송데이타의 증대에 유연하게 대처할 수 있다는 효과를 갖는다.The data transmission apparatus according to the present invention has the effect that it is possible to flexibly cope with the increase of the transmission data since the data can be transmitted without interposing the address bus by generating the addresses of the transmitting side and the receiving side in synchronization with the transmission clock signal. .

Description

데이타전송장치Data transmission device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 데이타전송장치를 보이는 블럭도이다, 제3도는 제2도에 도시된 장치의 데이타전송타이밍을 보이는 타이밍도이다.2 is a block diagram showing a data transmission apparatus according to the present invention, and FIG. 3 is a timing diagram showing the data transmission timing of the apparatus shown in FIG.

Claims (1)

제1메모리에 저장된 데이타를 독출하여 제2메모리에 격납시키는 데이타전송장치에 있어서, 리세트단자에 제공되는 데이타유효신호에 응답하여 활성화되어 클럭단자에 제공되는 전송클럭신호를 계수하고, 계수값을 상기 제1메모리의 독출어드레스로 제공하는 제1카운터; 클럭단자에 제공되는 전송클럭신호에 응답하여 상기 제1메모리에서 독출된 데이타를 래치하는 제1래치; 상기 제1래치와 상기 제2메모리 사이에 설치되어, 상기 제1래치에 의해 래치된 데이타를 상기 제2메모리에 제공하는 데이타버스; 리세트단자에 제공되는 데이타유효신호에 응답하여 활성화되어 클럭단자에 제공되는 전송클럭신호를 계수하고, 계수값을 상기 제2메모리의 기입어드레스로 제공하는 제2카운터; 데이타의 전송개시 및 종료를 나타내는 데이타유효신호를 발생하여 상기 제1카운터와 제2카운터의 리세트다나에 제공하고, 데이타전송을 지시하는 전송클럭신호를 발생하여 상기 제1카운터 및 제2카운터의 클럭단자와 상기 제1래치의 클럭단자에 제공하는 제어부를 포함하는 데이타전송장치.A data transmission apparatus for reading data stored in a first memory and storing the data in a second memory, the data transmission device being activated in response to a data valid signal provided to a reset terminal and counting a transmission clock signal provided to a clock terminal, and counting a count value. A first counter provided to the read address of the first memory; A first latch for latching data read from the first memory in response to a transmission clock signal provided to a clock terminal; A data bus provided between the first latch and the second memory to provide data latched by the first latch to the second memory; A second counter that is activated in response to the data valid signal provided to the reset terminal and counts the transmission clock signal provided to the clock terminal and provides the count value to the write address of the second memory; A data valid signal indicating the start and end of data transmission is generated and provided to the reset counters of the first counter and the second counter, and a transmission clock signal instructing data transmission is generated to generate the transmission counter signal of the first counter and the second counter. And a control unit provided to a clock terminal and a clock terminal of the first latch. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950000855A 1995-01-19 1995-01-19 Device for transmitting data KR100316310B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950000855A KR100316310B1 (en) 1995-01-19 1995-01-19 Device for transmitting data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950000855A KR100316310B1 (en) 1995-01-19 1995-01-19 Device for transmitting data

Publications (2)

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KR960029992A true KR960029992A (en) 1996-08-17
KR100316310B1 KR100316310B1 (en) 2002-02-19

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