KR960702674A - 플라즈마 처리방법(plasma processing method) - Google Patents

플라즈마 처리방법(plasma processing method)

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Publication number
KR960702674A
KR960702674A KR1019950705168A KR19950705168A KR960702674A KR 960702674 A KR960702674 A KR 960702674A KR 1019950705168 A KR1019950705168 A KR 1019950705168A KR 19950705168 A KR19950705168 A KR 19950705168A KR 960702674 A KR960702674 A KR 960702674A
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KR
South Korea
Prior art keywords
wafer
plasma
processing method
plasma processing
gas
Prior art date
Application number
KR1019950705168A
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English (en)
Other versions
KR100363340B1 (ko
Inventor
고 사이또
모또히꼬 요시가이
겐지 후지모또
Original Assignee
가나이 쯔도무
가부시키가이샤 히다치 세사쿠쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5118161A external-priority patent/JP2948053B2/ja
Priority claimed from JP11815693A external-priority patent/JPH08279487A/ja
Application filed by 가나이 쯔도무, 가부시키가이샤 히다치 세사쿠쇼 filed Critical 가나이 쯔도무
Publication of KR960702674A publication Critical patent/KR960702674A/ko
Application granted granted Critical
Publication of KR100363340B1 publication Critical patent/KR100363340B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32431—Constructional details of the reactor
    • H01J37/32798—Further details of plasma apparatus not provided for in groups H01J37/3244 - H01J37/32788; special provisions for cleaning or maintenance of the apparatus
    • H01J37/32853—Hygiene
    • H01J37/32862—In situ cleaning of vessels and/or internal parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/905—Cleaning of reaction chamber

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Epidemiology (AREA)
  • Public Health (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

본 발명은 높은 처리량을 가지며 에칭가스로 브롬화수소(HBr)를 사용하여 에칭하면서 정전기적 고정에 의해 전극에 웨이퍼를 지지하는 플라즈마 처리장치의 에칭실을 정정하는 방법을 제공하다. 에칭이 완료된 후 전극상에 정전지적으로 고정된 웨이퍼상의 정전하가 제거되는 경우, O2가스는 가스 유량제어장치로부터 에칭실로 유입된다. O2가스의 플라즈마가 생성되어, 웨이퍼상의 전하가 플라즈마를 통하여 접지로 흐르게 하며, 동시에 에칭실의 내부가 청정된다.

Description

플라즈마 처리방법(PLASMA PROCESSING METHOD)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 따른 플라즈마 처리방법의 일 실시예의 블록도.

Claims (9)

  1. 정전기력에 의해 실내의 전극상에 웨이퍼를 지지하면서 웨이퍼에 에칭처리를 실행하는 플라즈마 처리방법에 있어서: O2가스의 가스플라즈마를 사용하여 상기 웨이퍼상의 잔여 전하를 상기 플라즈마에 방진하여 비전화하여 상기 에칭처리가 완료된 후 상기 웨이퍼상에 잔재하는 잔여 청전기력을 제거하는 단계를 포함하는 것을 특징으로 하는 플라즈마 처리방법.
  2. 제1항에 있어서, 상기 에칭처리는 에칭가스로서 브롬화수소를 이용하는 단계를 포함하는 것을 특징으로 플라즈마 처리방법.
  3. 정전기력에 의해 실내의 전극상에 웨이퍼를 지지하면서 웨이퍼에 에칭처리를 실행하는 플라즈마 처리방법에 있어서: 실리콘-함유물질의 막이 브롬-함유가스의 플라즈마를 사용하여 에칭된 후 연속적으로 진공에서 O2및 CHF3를 함유하는 혼합가스의 플라즈마를 사용하여 상기 막을 후-처리하는 단계를 포함하는 것을 특징으로 하는 플라즈마 처리방법.
  4. 제3항에 있어서, 상기 브롬-함유가스는 HBr 및 O2의 혼합가스인 것을 특징으로 하는 플라즈마 처리방법.
  5. 제3항에 있어서, 상기 실리콘-함유물질의 막은 폴리-실리콘물질인 것을 특징으로 하는 플라즈마 처리방법.
  6. 제1항에 있어서, 상기 실리콘-함유물질의 막은 계단형 구조로 형성된 것을 특징으로 하는 플라즈마 처리방법.
  7. 청전기력에 의해 실내의 전극상에 웨이퍼를 지지하면서 웨이퍼에 에칭처리를 실행하는 플라즈마 처리방법에 있어서: 실리콘-함유물질의 막이 염소-함유가스의 플라즈마를 사용하여 에칭된 후 연속적으로 진공에서 O2및 CHF3를 함유하는 혼합가스의 플라즈마를 사용하여 상기 막을 후-처리하는 단계를 포함하는 것을 특징으로 하는 플라즈마 처리방법.
  8. 제7항에 있어서, 상기 실리콘-함유물질의 막은 폴리-실리콘물질인 것을 특징으로 하는 플라즈마 처리방법.
  9. 제7항에 있어서, 상기 실리콘-함유물질의 막은 계단형 구조로 형성되는 것을 특징으로 하는 플라즈마 처리방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950705168A 1993-05-20 1994-05-20 플라즈마처리방법 KR100363340B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP5118161A JP2948053B2 (ja) 1993-05-20 1993-05-20 プラズマ処理方法
JP93-118161 1993-05-20
JP93-118156 1993-05-20
JP11815693A JPH08279487A (ja) 1993-05-20 1993-05-20 プラズマ処理方法

Publications (2)

Publication Number Publication Date
KR960702674A true KR960702674A (ko) 1996-04-27
KR100363340B1 KR100363340B1 (ko) 2003-02-19

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Country Status (5)

Country Link
US (1) US5681424A (ko)
EP (2) EP0938134A3 (ko)
KR (1) KR100363340B1 (ko)
TW (1) TW255839B (ko)
WO (1) WO1994028578A1 (ko)

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EP0709877A4 (en) 1997-11-26
TW255839B (ko) 1995-09-01
EP0938134A2 (en) 1999-08-25
EP0938134A3 (en) 2000-01-19
US5681424A (en) 1997-10-28
WO1994028578A1 (fr) 1994-12-08
EP0709877A1 (en) 1996-05-01
KR100363340B1 (ko) 2003-02-19

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