KR950007075A - 반도체 장치 및 제조방법 - Google Patents

반도체 장치 및 제조방법 Download PDF

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Publication number
KR950007075A
KR950007075A KR1019940018378A KR19940018378A KR950007075A KR 950007075 A KR950007075 A KR 950007075A KR 1019940018378 A KR1019940018378 A KR 1019940018378A KR 19940018378 A KR19940018378 A KR 19940018378A KR 950007075 A KR950007075 A KR 950007075A
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South Korea
Prior art keywords
semiconductor device
thin film
substrate
semiconductor
wiring
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KR1019940018378A
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English (en)
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KR100332282B1 (ko
Inventor
미쯔오 우사미
다까시 다세
Original Assignee
가나이 쯔또무
가부시끼가이샤 히다찌세이사꾸쇼
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Publication of KR950007075A publication Critical patent/KR950007075A/ko
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Publication of KR100332282B1 publication Critical patent/KR100332282B1/ko

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/0772Physical layout of the record carrier
    • G06K19/07728Physical layout of the record carrier the record carrier comprising means for protection against impact or bending, e.g. protective shells or stress-absorbing layers around the integrated circuit
    • HELECTRICITY
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    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
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    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
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    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
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Abstract

신뢰성이 높고 저코스트인 반도체 장치에 관한 것으로서, 얇은 LSI를 사용한 IC카드에서 IC카드의 기계적 강도를 높이고 실장공정수를 저감해서 저코스트화를 도모하기 위해, 적어도 반도체 소자와 배선을 갖는 박막 반도체 장치에 있어서 반도체소자에 접촉하는 하면에 반도체 소자를 보호하기 위한 보호절연재료의 박막이 형성되고 보호절연막의 표면이 다른 기판에 접착되어 있으며, 반도체회로가 SOI웨이퍼상에 형성된 반도체회로의 박막, 이 박막 반도체회로를 반도체 회로가 형성되는 반대측에 접합하는 다른 기관, 이 다른 기판상에 미리 준비한 배선과 박막 반도체 회로의 배선과를 접속하는 경화성 도전재료로 이루어지는 것을 특징으로 한다.
이것에 의해, 보호절연막이 외부에 가장 가까운 반도체 소자의 이면으로부터 이온성 오염원이 침입하는 것을 방지하므로 신뢰성을 향상시킬 수가 있고, 얇은 LSI를 일반적으로 이온성 불순물이 다량 함유된 저렴한 유기 접착제를 사용해서 기판에 접착하는 것에 의해서 내구성을 향상시킬 수가 있고, 보호절연막으로서 질화실리콘을 사용하는 것에 의해 IC카드의 신뢰도가 향상한다는 효과가 얻어진다.
선택도;제6도

Description

반도체 장치 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명을 설명하기 위해 종래의 IC카드의 주요부를 도시한 도면.
제5도는 종래구조의 기판두계가 두꺼운 IC카드의 구부러진 상태를 도시한 단면도.
제6도는 본 발명의 실시예에 따른 반도체 장치의 주요부를 도시한 단면도.

Claims (17)

  1. 적어도 반도체 소자와 배선을 갖는 박막 반도체 장치에 있어서, 상기 반도체 소자의 하면에 형성된 보호절연재료의 박막과 상기 박막의 하면에 접착된 기판을 갖는 것을 특징으로 하는 반도체 장치.
  2. 제1항에 있어서, 상기 박막 반도체 장치는 실리콘 온 인슐레이터 웨이퍼상에 형성된 반도체 회로의 박막이고, 상기 기판은 박막 반도체 회로의 반도체 회로가 형성된 반대면에 접합되고, 또 상기 기판에 미리 마련된 배선과 상기 반도체 회로의 회선을 상호 접속하는 경화성 도전재료를 포함하는 것을 특징으로 하는 반도체 장치.
  3. 제2항에 있어서, 상기 반도체 소자는 상기 실리콘 온 인슐레이터 웨이퍼의 안쪽의 절연층을 경계로 해서 상기 실리콘 온 인슐레이터 웨이퍼의 주면측으로부터 인출된 박막 반도체 회로인 것을 특징으로 하는 반도체 장치.
  4. 제1항에 있어서, 상기 반도체 소자의 하면에 형성된 보호절연재료의 박막과 상기 기판은 서로 고무형상의 접착제에 의해 접합된 것을 특징으로 하는 반도체 장치.
  5. 제2항에 있어서, 상기 반도체 장치의 주면측이 지지기판에 접착된 후, 실리콘 온 인슐레이터 웨이퍼 기판이 연삭 또는 애칭에 의해 제거되는 것을 특징으로 하는 반도체 장치.
  6. 제1항에 있어서, 상기 보호 절연재료의 박막의 하면에 접착되는 상기 기판은 가요성이 있는 카드형상의 기판인 것을 특징으로 하는 반도체 장치.
  7. 제5항에 있어서, 상기 지지기판은 가요성이 있는 지지기판인 것을 특징으로 하는 반도체 장치.
  8. 제5항에 있어서, 상기 반도체 장치는 자외선 박리성의 접착제에 의해 상기 지지기판에 접착된 것을 특징으로 하는 반도체 장치.
  9. 제2항에 있어서, 상기 경화성 도전재료는 회전드럼에 의한 인쇄배선에 의해서 형성되는 것을 특징으로 하는 반도체 장치.
  10. 제1항에 있어서, 상기 보호절연재료의 박막의 하면에 접착된 기판과 동일한 두께를 갖는 기판은 상기 반도체 소자의 상면에 접착되는 것을 특징으로 하는 반도체 장치.
  11. 제10항에 있어서, 상기 반도체 소자는 상기 보호절연재료의 박막의 하면에 접착된 기판의 이면과 상기 반도체 소자의 상면에 접착된 기판의 표면으로부터 등거리로 배치된 것을 특징으로 하는 반도체 장치.
  12. 제10항에 있어서, 상기 반도체 자치의 두계가 760미크론 이상일 때 상기 박막 반도체소자의 두께는 110미크론 이하이고, 상기 반도체 장치의 두계가 500미크론 이상일 때 상기 박막 반도체 소자의 두께는 이하이며, 또 상기 반도체 장치의 두꼐가 250미크론 이상일 때 상기 박막 반도체 소자가 4미크론 이하로 되도록 구성된 것을 특징으로 하는 반도체 장치.
  13. 제10항에 있어서, 상기 반도체 장치의 두께가 250미크론 이하인 경우, 적어도 상기 박막 반도체 소자의 두께는 4미크론 이하로 되도록 구성된 것을 특징으로 하는 반도체 장치.
  14. 제10항에 있어서, 상기 박막 반도체 장치는 가요성이 있는 접착제에 의해서 상기 쌍방의 카드기판에 접착된 것을 특징으로 하는 반도체 장치.
  15. 제1항에 있어서, 상기 보호절연재료는 질화 실리콘인 것을 특징으로 하는 반도체 장치.
  16. 반도체 소자와 배선을 갖는 박막 반도체 장치의 제조방법으로서, 실리콘 온 인슐레이터 웨이퍼상에 박막반도체 회로를 형성하는 공정, 상기 실리콘 온 인슐레이터 웨이퍼의 이면으로부터 실리콘 기판을 에칭제거하는 공정, 박막 반도체 칩을 형성하는 공정, 이렇게 해서 형성된 박막 반도체 칩을 기판에 부착하는 공정 및 박막 반도체 칩과 기판 사이를 인쇄기술에 의해서 배선하는 공정을 포함하는 것을 특징으로 하는 박막 반도체 장치의 제조방법.
  17. 제16항에 있어서, 상기 인쇄기술에 의해 배선하는 공정에 있어서 회전드럼에 소정의 배선패턴의 도전성 잉크를 전사하고, 상기 회전드럼에 전사되는 도전성 잉크의 배선패턴을 상기 기판과 상기 기판에 부착된 박막 반도체 칩에 전사하는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
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EP0637841A2 (en) 1995-02-08
KR100332282B1 (ko) 2002-09-04
US6291877B1 (en) 2001-09-18
KR100332285B1 (ko) 2002-04-12
DE69434234D1 (de) 2005-02-17
EP0637841A3 (en) 1995-11-29
KR100332284B1 (ko) 2002-04-12
US5689136A (en) 1997-11-18
EP0862134A2 (en) 1998-09-02
US6051877A (en) 2000-04-18
US20020027274A1 (en) 2002-03-07
US6486541B2 (en) 2002-11-26

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