KR890005830A - 반도체 장치 및 그 제조방법 - Google Patents

반도체 장치 및 그 제조방법 Download PDF

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KR890005830A
KR890005830A KR1019880011804A KR880011804A KR890005830A KR 890005830 A KR890005830 A KR 890005830A KR 1019880011804 A KR1019880011804 A KR 1019880011804A KR 880011804 A KR880011804 A KR 880011804A KR 890005830 A KR890005830 A KR 890005830A
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sheet
chips
semiconductor device
memory
terminal
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KR1019880011804A
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류우따로우 아라까와
스나오 후꾸따께
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나가이 아쯔시
히다찌마구세루 가부시기가이샤
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Publication of KR890005830A publication Critical patent/KR890005830A/ko

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

내용 없음

Description

반도체 장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체 장치의 1실시예를 도시한 평면도.
제2도는 제1도에서의 그 단면도.
제3도는 제2도에 있어서 IC를 내장한 경우의 단면도.

Claims (9)

  1. 여러개의 접속단자(53∼58)과 상기 여러개의 접속단자의 적어도 1개의 접속단자에 접속된 리이드단자(9,51,52)를 갖는 시이트(1)과 상기 접속단자에 그 외부 리이드가 본딩되어서 상기 시이트상에서 탑재된 테이프오토 본딩법에 의한 여러개의 IC칩(8)를 구비 하는 시이트 모듈(6)을 상기 리이드단자를 거쳐서 기판의 단자에 접속한 것을 특징으로 하는 반도체 장치.
  2. 특허청구의 범위 제 1항에 있어서 상기 IC칩은 메모리 IC칩이고, 상기 여러개의 접속 단자의 몇개인가가 시이트에 형성된 배선패턴에 의해 접속되어 있고, 여러개의 상기 메모리 IC칩은 시이트의 표면과 이면에 탑재되어 표면과 이면의 대응 하는 접속단자가 스루홀(7)로 접속되어 있는 것을 특징으로 하는 반도체 장치.
  3. 특허청구의 범위 제 2항에 있어서 , 상기 여러개의 IC칩은 모두 동일형식의 메모리 IC칩이고 상기 여러개의 메모리 IC칩은 시이트를 거쳐서 상하로 겹치도록 시이트의 표면과 이면에 각각 1단식 상하 1쌍의 메모리 IC칩이 같은 방향을 향하도록 탑재되어 있는 것을 특징으로 하는 반도체 장치.
  4. 특허청구의 범위 제 3항에 있어서, 상기 시이트에 탑재되는 상기 여러개의 메모리 IC칩은 4개 이상의 짝수인 것을 특징으로 하는 반도체 장치.
  5. 특허청구의 범위 제 3항에 있어서, 상기 시이트에 탑재되는 상기 여러개의 메모리 IC칩은 내부리이드의 본딩면이 수지(11)로 덮어져 있는 것을 특징으로 하는 반도체 장치.
  6. 특허청구의 범위 제 1항에 있어서, 상기 시이트는 테이프에서 떼어낸 막인 것을 특징으로 하는 반도체 장치.
  7. 특허청구의 범위 제 3항에 있어서, 상기 시이트는 폴리이미드 또는 글라스 에폭시 수지의 두께 18㎛∼125㎛의 플랙시블 테이프인 것을 특징으로 하는 반도체 장치.
  8. 특허청구의 범위 제 1항에 있어서, 여러개의 상기 시이트 모듈은 기판(15)의 표면과 이면에 탑재되고, 표면과 이면의 대응하는 단자가 스루홀(16)으로 접속되어 있는 것을 특징으로 하는 반도체 장치.
  9. 테이프 양쪽면에 금속을 피복하고, 표면과 이면에 도통 하는 스루홀을 형성하여 에칭으로 상기 스루홀에 접속되도록 여러개의 접속단자와 상기 여러개의 접속단자의 적어도 1개에 접속되도록 리이드단자를 형성하고, 상기 접속단자 및 리이드단자 이외의 부분을 절연처리하고 절연처리하지 않은 부분에 금속 피복 하는 공정, 테이프 오토 본딩법에 의해 조립된 여러개의 IC칩을 상기 접속단자에 그 외부리이드를 본딩해서 상기 테이프에 탑재하여 모듈부분을 형성 하는 공정 및 상기 모듈부분을 상기 테이프에서 떼어내서 상기 리이드단자를 기판의 단자에 접속하여 상기 기판에 탑재 하는 공정을 구비한 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880011804A 1987-09-21 1988-09-13 반도체 장치 및 그 제조방법 KR890005830A (ko)

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Application Number Priority Date Filing Date Title
JP62236891A JPS6480032A (en) 1987-09-21 1987-09-21 Semiconductor device and manufacture thereof
JP62-236891 1987-09-21

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KR0127678B1 (ko) 1998-04-03

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