KR940022755A - 반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame) - Google Patents

반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame) Download PDF

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Publication number
KR940022755A
KR940022755A KR1019940005376A KR19940005376A KR940022755A KR 940022755 A KR940022755 A KR 940022755A KR 1019940005376 A KR1019940005376 A KR 1019940005376A KR 19940005376 A KR19940005376 A KR 19940005376A KR 940022755 A KR940022755 A KR 940022755A
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South Korea
Prior art keywords
semiconductor device
lead
stage
metal film
regions
Prior art date
Application number
KR1019940005376A
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English (en)
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KR0119464B1 (en
Inventor
쓰지 가즈또
요네다 요시유끼
사꼬다 히데하루
소노 미찌오
야마구찌 이찌로
하마노 도시오
구보따 요시히로
하야까와 미찌오
이께모또 요시히꼬
사이고 유끼오
미야지 나오미
Original Assignee
세끼사와 다까시
후지쓰 가부시끼가이샤
미야따 유다까
가부시끼가이샤 규슈 후지쓰 일렉트로닉스
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP5056252A external-priority patent/JPH06268091A/ja
Priority claimed from JP5057527A external-priority patent/JPH06275761A/ja
Priority claimed from JP6020642A external-priority patent/JPH07231069A/ja
Application filed by 세끼사와 다까시, 후지쓰 가부시끼가이샤, 미야따 유다까, 가부시끼가이샤 규슈 후지쓰 일렉트로닉스 filed Critical 세끼사와 다까시
Publication of KR940022755A publication Critical patent/KR940022755A/ko
Application granted granted Critical
Publication of KR0119464B1 publication Critical patent/KR0119464B1/ko

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Abstract

반도체 장치가 밀봉되는 패키지를 갖는 반도체 장치는 베이스를 포함하고 금속막이 베이스의 표면에 형성된다.
반도체 칩은 금속막상에 형성된다. 반도체 칩상에 형성된 패드는 배선에 의해 그속막에 접속된다. 밀봉층은 금속막상에 형성된다. 접속층은 금속막상에 형성되어 전기적 전도성 입자를 포함한다. 접속층은 전원 시스텝용 리드와 접촉하고 금속막을 리드에 접속한다.

Description

반도체 장치 및 그 제조방법과 반도체장치용 리드프레임(Lead frame)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명의 제1실시예에 따른 반도체 장치의 단면도.
제5도는 제4도에 도시된 반도체 장치의 일부 평면도.
제6도는 제4도에 도시된 구조의 제1변형물에 따른 반도체 장치의 단면도.

Claims (58)

  1. 반도체장치가 밀봉되는 패키지를 갖는 반도체 장치에 있어서, 베이스, 베이스 표면에 형성된 금속막, 반도체 칩은 금속막에 형성되고 반도체 칩상에 형성된 패드는 배선에 의해 금속막에 접속되며, 금속막상에 형성된 밀봉층, 유리층상에 형성된 리드, 및 금속막상에 형성되어 전기적 전도성 입자를 포함하고, 전원시스템용 리드와 접촉하여 상기 리드에 금속막을 접속하는 접속층으로 구성되는 반도체 장치.
  2. 제1항에 있어서, 밀봉층의 상부 표면이 접속층의 상부표면과 대략 동일한 레벨에서 위치되는 반도체 장치.
  3. 제1항에 있어서, 상기 전원시스템용 리드가 밀봉층 상부보다 낮은 레벨에서 위치된 구부러진 단부를 갖고 접속층이 상기 리드의 구부러진 단부와 접촉하여 있는 반도체 장치.
  4. 제1항에 있어서, 상기 베이스는 접속층이 금속막을 거쳐 위치되는 돌출부를 갖는 반도체 장치.
  5. 제1항에 있어서, 전원시스템용 리드가 접속층과 접촉하는 단부를 갖고, 상기 단부가 접속층과 접착을 용이하게 하는 조면을 갖는 반도체 장치.
  6. 제1항에 있어서, 전원시스템용 리드가 접속층과 접촉하는 단부를 갖고, 상기간부가 접속층과 접착을 용이하게 하는 다수의 딤플을 갖는 반도체 장치.
  7. 제1항에 있어서, 전원시스템용 리드가 접속층과 접촉하는 단부를 갖고, 상기 단부가 접속층과 접착을 용이하게 하는 다수의 통공을 갖는 반도체 장치.
  8. 제1항에 있어서, 접속층이 전기적 전도성입자를 포함하는 내화성유리층으로 구성되는 반도체 장치.
  9. 제1항에 있어서, 베이스가 세라믹물질로 구성되는 반도체 장치.
  10. 반도체 장치가 밀봉되는 패키지를 갖는 반도체 장치에 있어서, 베이스, 베이스 표면에 형성된 금속막, 상기 금속막은 다수의 분리된 영역을 갖고 반도체 칩은 다수의 분리된 영역중 한 영역에 형성되고, 금속막상에 형성된 밀봉층, 유리층상에 형성된 리드, 및 반도체 칩상에 형성된 패드를 리드와 다수의 분리된 영역에 접속하고 리드를 다수의 분리된 영역에 접촉하는 배선으로 접속층으로 구성되는 반도체 장치.
  11. 제10항에 있어서, 다수의 분리된 영역이 전원선과 접지선으로 구성되는 전원시스템을 형성하는 반도체 장치.
  12. 제10항에 있어서, 반도체 칩상에 형성된 패드중의 하나와 리드 또는 분리된 영역중 하나가 다수의 배선 또는 상기 다수의 배선의 직경의 합과 대략같은 직경을 갖는 단일 배선에 의해 접속되며, 분리된 영역중 하나와 리드중 하나가 다수의 배선 또는 상기 다수의 배선의 직경의 합과 대략 같은 직경을 갖는 단일 배선에 의해 접속되는 반도체 장치.
  13. 제10항에 있어서, 리드가 밀봉층과 접촉하는 첫 번째 부분과 배선이 접속되는 두 번째 부분에 형성된 금속막으로 구성되는 반도체 장치.
  14. 제10항에 있어서, 유리층이 밀봉층에서 분리되고 개구가 유리층과 밀봉층사이에 형성되도록 금속막상에 형성된 유리층과 상기 개구를 통하여 연장되는 금속막의 분리된 영역과 리드를 접속하는 배선으로 더 구성되는 반도체 장치.
  15. 제10항에 있어서, 상기 리드가 전원시스템 리드와 신호시스템 리드로 구성되고 전원 시스템 리드가 신호시스템 리드보다 넓고 짧은 반도체 장치.
  16. 제10항에 있어서, 금속막의 분리된 영역의 제1영역이 금속막의 분리된 영역의 제2영역에 의해 둘러싸여지도록 형성되는 반도체 장치.
  17. 제16항에 있어서, 상기 분리된 영역의 제1영역이 전원시스템의 제1전위를 갖고 상기 분리된 영역의 제2영역이 제2전위를 갖는 반도체 장치.
  18. 제10항에 있어서, 반도체 칩이 설치되는 금속막의 상기 분리된 영역 중 한 영역을 제외한 다수의 영역이 상기 분리된 영역중 한 영역을 둘러싸도록 위치되는 반도체 장치.
  19. 제10항에 있어서, 배선이 반도체 칩상에 형성된 패드를 신호 시스템 리드에 접속하기 위한 제1배선과 금속막의 분리된 영역을 반도체 칩 상에 형성된 패드에 접속하기 위한 제2배선으로 구성되며, 상기 제2배선이 제1배선보다 짧은 반도체 장치.
  20. 제10항에 있어서, 리드가 신호 시스템 리드와 전원 시스템 리드로 구성되고, 반도체 장치가 금속막상에 형성된 유리층으로 구성되며, 신호 시스템리드의 단부가 유리층상에 설치되는 반도체 장치.
  21. 제20항에 있어서, 상기 유리층이 다수의 분리된 영역으로 구성되는 반도체 장치.
  22. 제10항에 있어서, 리드가 신호 시스템 리드와 전원시스템 리드로 구성되고, 반도체 장치가 금속막상에 형성된 결정질 내화성 유리층으로 구성되고, 신호 시스템 리드의 단부가 결정질 내화성 유리층상에 설치되며, 밀봉층이 비정질 내화성 유리층으로 구성되는 반도체 장치.
  23. 제10항에 있어서, 베이스가 리세스부로 구성되며, 금속막이 리세스부와 베이스의 상부의 바닥면에 형성되는 반도체 장치.
  24. 제10항에 있어서, 베이스가 적어도 한 단계 부분을 갖는 리세스부로 구성되며, 금속막이 리세스부, 상기 적어도 한 단계 부분, 및 베이스의 상부의 바닥면에 형성되는 반도체 장치.
  25. 제10항에 있어서, 밀봉층에 접속된 캡으로 더 구성되는 반도체 장치.
  26. 제25항에 있어서, 반도체 장치를 인해 인쇄 회로판에 설치할 때 베이스가 인쇄 회로판에 접하도록 리드가 구부려진 부분으로 구성되는 반도체 장치.
  27. 제25항에 있어서, 반도체 장치를 인쇄회로판에 설치할 때 캡이 인쇄회로판에 접하도록 리드가 구부려진 부분으로 구성되는 반도체 장치.
  28. 제10항에 있어서, 베이스가 세라믹 물질로 구성되는 반도체 장치.
  29. 제27항에 있어서, 금속부재가 형성되는 표면에 반대쪽 베이스의 표면에 설치된 열 방사부재로 더 구성되는 반도체 장치.
  30. 반도체 장치가 밀봉되는 패키지를 갖는 반도체 장치에 있어서, 다수의 분리된 영역을 갖는 스테이지, 반도체 칩이 다수의 분리된 영역중 한 영역에 형성되고, 분리된 영역이 패키지의 수지에 의해 지지되고, 반도체 칩이 설치되는 스테이지의 표면에 반대쪽 스테이지의 배면이 패키지로부터 노광되고, 스테이지가 전기적 전도성 물질을 포함하며, 패키지로부터 연장되는 리드, 및 반도체 칩상에 형성된 패드를 리드와 분리된 영역에 접속하는 배선으로 구성되는 반도체 장치.
  31. 제30항에 있어서, 분리된 영역이 동심적으로 배열되는 반도체 장치.
  32. 제30항에 있어서, 스테이지와 리드가 일체로 형성된 리드 프레임의 부분인 반도체 장치.
  33. 제30항에 있어서, 반도체 칩이 설치되는 분리된 영역 중 한 영역과 다른 분리된 영역중 적어도 한 영역이 다수의 분리된 영역으로 구성되는 반도체 장치.
  34. 제30항에 있어서, 리드가 스테이지를 겹치는 단부를 갖는 리드로 구성되는 반도체 장치.
  35. 제34항에 있어서, 스테이지상에 형성되고 상기 리드의 단부를 지지하는 절연 접착테이프로 더 구성되는 반도체 장치.
  36. 제30항에 있어서, 리드가 스테이지를 겹치고 스테이지와 직접 접촉하는 단부를 갖는 리드로 구성되는 반도체 장치.
  37. 제30항에 있어서, 스테이지의 분리된 영역에 리드를 접속하는 배선으로 더 구성되는 반도체 장치.
  38. 제30항에 있어서, 반도체 칩이 설치되는 분리된 영역 중 한 영역이 다수의 분리된 영역으로 구성되는 반도체 장치.
  39. 제30항에 있어서, 리드의 배면에 형성되고, 반도체 장치를 인쇄회로판에 설치할 때 인쇄회로판에 형성된 패턴에 전기적으로 접속되는 전극으로 더 구성되는 반도체 장치.
  40. 제39항에 있어서, 전극이 땜납범프로 구성되는 반도체 장치.
  41. 제30항에 있어서, 반도체 장치를 인쇄회로판상에 설치할 때 스테이지의 배면이 인쇄회로판에 접하도록 리드가 구부려진 부분으로 구성되는 반도체 장치.
  42. 제30항에 있어서, 반도체 장치를 인쇄회로판상에 설치할 때 스테이지의 배면이 위로 접하도록 리드가 구부려진 부분으로 구성되는 반도체 장치.
  43. 제42항에 있어서, 스테이지의 배면에 설치된 옆방사부재로 더 구성되는 반도체 장치.
  44. 제30항에 있어서, 스테이지의 분리된 영역이 접지를 포함하는 전원시스템에 사용되는 반도체 장치.
  45. 제30항에 있어서, 상기 패키지가 플라스틱 패키지로 구성되는 반도체 장치.
  46. 제30항에 있어서, 리드가 보호막으로 도포된 외부리드부로 구성되는 반도체 장치.
  47. 반도체 칩이 설치되는 표면을 갖는 스테이지, 내부 리드부와 외부 리드부를 갖는 리드, 상기 스테이지는 스테이지의 상기 표면에 형성된 홈을 가지며, 홈은 리드 프레임이 패키지된 반도체 장치에 제공되는 상태에서 서로 분할된 영역으로 스테이지를 규정하는 패키지된 반도체 장치용 리드 프레임.
  48. 제47항에 있어서, 스테이지와 리드가 리드 프레임의 일체로 형성된 부분인 리드 프레임.
  49. 제47항에 있어서, 리드가 스테이지를 겹치는 단부를 갖는 리드 프레임.
  50. 제47항에 있어서, 반도체 칩이 설치되는 스테이지의 영역중 한 영역과 다른 스테이지의 영역중 적어도 한 영역이 패키지된 반도체 장치에 리드 프레임을 제공하는 상태에서 분할된 영역으로 스테이지의 영역중 상기 적어도 한 영역을 분할하는 제2홈을 갖는 리드 프레임.
  51. 제47항에 있어서, 리드가 스테이지를 겹치는단부를 갖고 절연 접착 테이프에 의해 단부에 고정되는 리드 프레임.
  52. 제49항에 있어서, 스테이지를 겹치는 리드의 단부가 스테이지와 직접 접촉하는 리드 프레임.
  53. 제47항에 있어서, 외부 리드부가 보호막으로 도포되는 리드 프레임.
  54. 제47항에 있어서, 반도체 칩이 스테이지의 영역중 한 영역에 설치되고, 스테이지의 영역중 상기 한 영역이 반도체 칩을 설치하는 표면에 제2홈을 가지며, 상기 제2홈이 패키지된 반도체 장치에 리드프레임을 제공하는 상태에서 서로 분리된 영역으로 스테이지의 영역중 상기 한 영역을 분할하는 리드 프레임.
  55. (a) 리드 프레임의 스테이지의 제1표면에 반도체 칩을 설치하고, 상기 스테이지는 스테이지의 제1표면에 형성된 홈을 가지고, (b) 반도체 칩, 스테이지와 리드사이에 전기적 접속을 행하고, (c) 반도체 칩을 밀봉하는 패키지를 형성하고, (d) 패키지의 표면을 제거하고, 제1표면에 반대쪽 스테이지의 제2표면이 나타나게 하여 스테이지의 영역을 서로 분리하는 단계로 구성되는 반도체 장치의 제조방법.
  56. 제55항에 있어서, 리드의 외부리드부를 금속막으로 도금하는 단계(e)로 더 구성되는 방법.
  57. 제55항에 있어서, 스테이지의 제2표면에 범프전극을 형성하는 단계(e)로 더 구성되는 방법.
  58. 제55항에 있어서, 스테이지의 제2표면에 열방사 부재를 부착하는 단계(e)로 더 구성되는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR19940005376A 1993-03-17 1994-03-17 Semiconductor device and lead frame KR0119464B1 (en)

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JP93-56252 1993-03-17
JP5056252A JPH06268091A (ja) 1993-03-17 1993-03-17 半導体装置
JP5057527A JPH06275761A (ja) 1993-03-17 1993-03-17 半導体装置
JP94-20642 1994-02-17
JP6020642A JPH07231069A (ja) 1994-02-17 1994-02-17 半導体装置及びその製造方法及びこれに使用されるリードフレーム

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