KR940001363A - 로우 프로필 오버몰드된 패드 배열 반도체 디바이스 및 그 제조방법 - Google Patents

로우 프로필 오버몰드된 패드 배열 반도체 디바이스 및 그 제조방법 Download PDF

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KR940001363A
KR940001363A KR1019930009964A KR930009964A KR940001363A KR 940001363 A KR940001363 A KR 940001363A KR 1019930009964 A KR1019930009964 A KR 1019930009964A KR 930009964 A KR930009964 A KR 930009964A KR 940001363 A KR940001363 A KR 940001363A
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holes
semiconductor device
metal traces
semiconductor die
pattern
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더블유. 슬로앤 제임스
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빈센트 비, 인그라시아
모토로라 인코포레이티드
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Abstract

로우 프로필 오버몰드된 패드 배열 캐리어 (48)는 한면에서 금속을 가지며 도금되지 않은 스루홑을 갖는 신규한 기판(40)을 이용하여 제조된다. 신균한 기판은 어느 한면에 땜납 레지스터층의 필요성을 제거한다. 반도체 다이(50)는 기관의 상단면에 부착되고 기판에서 금속 트레이스(46)에 와이어 본딩된다. 패키지 몸체 (54)는 최소한 다이와 와이어 본드 (52)를 덮으며 기관에 오버몰드된다. 땜 납볼 (56)은 스루홀 (44) 내에 부착되며, 따라서 기판의 상단면에서 금속 트레이스에 직접 연결된다.

Description

로우 프로필 오버몰드된 패드 배열 반도체 디바이스 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명의 실시예에 의한 로우 프로필 오브몰드된 패드 배열 캐리어를 위한 개량된 기판의 평면도, 제6도는 본 발명의 따른 실시예에 의하여 로우 프로필 오브 몰드된 패드 배열 캐리어를 위한 다른 기판의 횡단면도.

Claims (3)

  1. 로우 프로필 오버몰드된 반도체 디바이스(48)에 있어서, 기판(40)은 제1면과, 제2면과 다수의 스루홀(44)을 가지고, 다만 제1면이 다수의 스루홀을 덮는 다수의 땜납 패드(47)에서 종단하는 도전성 금속 트레이스(46)의 패턴을 가지고, 반도체 다이 (50)는 제 1면에 부착되며 도전성 금속 트레이스의 패턴에 전기 직으로 접속되고 패키지 몸체 (54)는 최소한 반도체 다이를 덮는 캡슬봉입 재료에 외해 형성되고, 다수의 땜납불 (56)은 제2면에서 연장하며 다수의 스루홀을 경유하여 제1면에서 다수의 땜납 패드에 연결되는 구성을 갖는 것을 특징으로 하는 반도체 디바이스.
  2. 로우 프로필 오버몰드된 반도체 디바이스(48)에 있어서, 인쇄 회로판(40)은 제1면과. 제2면과 다수의 스루홀(44)을 가지고, 다만 제1면이 다수의 스루홀을 덮는 다수의 땜납 패드(47)에서 종단하는 도전성 금속 트레이스(46)의 패턴을 가지며, 또 0.165㎜내지 0.3㎜의 범위에서 두께를 가지고 반도체 다이 (50)는 제1면에 부착되고,
    다수의 와이어 본드(52)는 반도체 다이를 도전성 금속 트레이스의 패턴에 전기적으로 접속시키고, 패키지 몸체(54)는 최소한 반도체 다이를 덮는 캡슬 봉입 재료에 의해 형성되고, 다수의 땜납볼(56)은 제2면에서 연장하며 다수의 스루홀을 경유하여 제1면에서 다수의 땜납 패드에 연결되는 구성을 갖는 것을 특징으로 하는 반도체 디바이스.
  3. 로우 프로필 오버몰드된 반도체 디바이스(40)의 제조방법에 있어서, 제1면과 제2면과 다수의 스루홀을 가지며 또 다만 제1면이 다수의 스루홀을 덮는 다수의 땜납 패드에서 종단하는 도전성 금속 트레이스의 패턴을 갖는 것으로 구성된 기판 (40)을 제공하는 단계와, 제 1면에 반도체 다이 (50)를 부착하는 단계와, 반도체 다이 를 도전성 금속 트레이스의 패턴에 전기적으로 접속하는 단계와, 최소한 반도체 다이를 덮기 위해 캡슬 봉입 재료로서 패키지 몸체 (54)를 형성하는 단계와, 기판의 제2면에서 연장하는 다수의 땜납볼을 수의 땜납 패드에 연결하기 위해 다수의 스루홀에서 다수의 땜납볼(56)를 부착하는 단계를 구비하는 것을 특징으로 하는 반도체 디바이스의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930009964A 1992-08-06 1993-06-03 로우 프로필 오버몰드된 패드 배열 반도체 디바이스 및 그 제조방법 KR940001363A (ko)

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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100437437B1 (ko) 1994-03-18 2004-06-25 히다치 가세고교 가부시끼가이샤 반도체 패키지의 제조법 및 반도체 패키지
US5467253A (en) * 1994-06-30 1995-11-14 Motorola, Inc. Semiconductor chip package and method of forming
CA2154409C (en) * 1994-07-22 1999-12-14 Yuzo Shimada Connecting member and a connecting method using the same
JPH0878472A (ja) * 1994-09-05 1996-03-22 Hitachi Cable Ltd 半導体装置用基体および半導体装置
JP2682499B2 (ja) * 1995-03-09 1997-11-26 日本電気株式会社 半導体装置
JP3264147B2 (ja) * 1995-07-18 2002-03-11 日立電線株式会社 半導体装置、半導体装置用インターポーザ及びその製造方法
JPH0945805A (ja) * 1995-07-31 1997-02-14 Fujitsu Ltd 配線基板、半導体装置及び半導体装置を配線基板から取り外す方法並びに半導体装置の製造方法
JP3392992B2 (ja) * 1995-08-11 2003-03-31 日立化成工業株式会社 半導体パッケージ
JP3529507B2 (ja) * 1995-09-04 2004-05-24 沖電気工業株式会社 半導体装置
JP3176542B2 (ja) * 1995-10-25 2001-06-18 シャープ株式会社 半導体装置及びその製造方法
JP3445895B2 (ja) * 1996-02-28 2003-09-08 日立化成工業株式会社 半導体パッケ−ジ用チップ支持基板
JPH09260436A (ja) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp 半導体装置
US6093971A (en) * 1996-10-14 2000-07-25 Fraunhofer-Gesellschaft Zur Forderung Der Angewandten Forschung E.V. Chip module with conductor paths on the chip bonding side of a chip carrier
US5989935A (en) * 1996-11-19 1999-11-23 Texas Instruments Incorporated Column grid array for semiconductor packaging and method
TW351008B (en) 1996-12-24 1999-01-21 Matsushita Electronics Corp Lead holder, manufacturing method of lead holder, semiconductor and manufacturing method of semiconductor
US6215184B1 (en) * 1998-02-19 2001-04-10 Texas Instruments Incorporated Optimized circuit design layout for high performance ball grid array packages
US5929522A (en) 1998-04-17 1999-07-27 Hestia Technologies, Inc. Semiconductor non-laminate package and method
JP4151136B2 (ja) 1998-06-15 2008-09-17 松下電器産業株式会社 基板および半導体装置とその製造方法
JP2001156212A (ja) 1999-09-16 2001-06-08 Nec Corp 樹脂封止型半導体装置及びその製造方法
JP3760913B2 (ja) * 2002-11-29 2006-03-29 日立化成工業株式会社 半導体パッケージ用基板
JP2005005409A (ja) 2003-06-11 2005-01-06 Matsushita Electric Ind Co Ltd 半導体装置
CN103474363B (zh) * 2013-09-26 2016-09-21 华进半导体封装先导技术研发中心有限公司 一种基于有机基板技术的封装工艺及封装结构
IT201700073501A1 (it) 2017-06-30 2018-12-30 St Microelectronics Srl Prodotto a semiconduttore e corrispondente procedimento

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4700473A (en) * 1986-01-03 1987-10-20 Motorola Inc. Method of making an ultra high density pad array chip carrier
CA2095609C (en) * 1990-12-21 1996-11-26 William B. Mullen, Iii Leadless pad array chip carrier

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