KR930001365A - 복합 플립 칩 반도체 소자와 그 제조 및 번-인(burning-in) 방법 - Google Patents

복합 플립 칩 반도체 소자와 그 제조 및 번-인(burning-in) 방법 Download PDF

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KR930001365A
KR930001365A KR1019920010970A KR920010970A KR930001365A KR 930001365 A KR930001365 A KR 930001365A KR 1019920010970 A KR1019920010970 A KR 1019920010970A KR 920010970 A KR920010970 A KR 920010970A KR 930001365 A KR930001365 A KR 930001365A
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biases
electrically connected
interposer
flip chip
semiconductor device
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KR1019920010970A
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티. 린 파울
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빈센트 죠셉 로너
모토로라 인코포레이티드
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Publication of KR930001365A publication Critical patent/KR930001365A/ko

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    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
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Abstract

내용 없음

Description

복합 플립 칩 반도체 소자와 그 제조 및 번-인(BURNING-IN) 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 복합 플립 칩 반도체 소자를 형성하도록 본 발명에 따라 인터포우터(interposer)에 부착된 반도체 다이의 사시도.
제2도는 반도체 소자를 인티포우저상에 위치시킨 후의 제1도 반도체 소자의 평면도.
제3도는 제2도 반도체 소자의 저면도.
제4도는 제2도의 라인 4-4를 따라 취해진 반도체 소자의 단면도.

Claims (3)

  1. 복합 플립 칩 반도체 소자(10)에 있어서; 그 위에 형성된 직접 회로와 직접 회로에 전기적으로 연결된 다수의 본딩 패드(14)를 가지는 단일 반도체 다이(12)와; 제1 및 제2 표면과 제1표면에서 제2표면으로 확장하는 다수의 바이어스를 가지며, 제1표면이 상기 다수의 바이어스에 전기적으로 연결된 다수의 도전 트레이스(26)를 가지는 인터포우저; 상기 다수의 본딩 패드를 상기 다수의 도전 트레이스에 전기적으로 연결시키는 수단; 및 상기 다수의 바이어스를 기판에 전기적으로 연결시키는 수단을 구비하는 복합 플립 칩 반도체 소자.
  2. 복합 플립 칩 반도체 소자(10)를 제조하는 방법에 있어서; 제1 및 제2 상반된 표면과 그 위에 형성된 집적회로를 가지며, 제1표면이 직접 회로에 전기적으로 연결된 다수의 본딩 패드(14)를 가지는 반도체 다이(12)를 제공하며; 제1 및 제2상반된 표면과 제1표면에서 제2표면으로 확장하는 다수의 전기적 바이어스(24)를 가지며, 제1표면이 상기 다수의 바이어스에 전기적으로 연결된 다수의 전기적 트레이스(26)를 가지는 인터포우저(22)를 제공하고; 반도체 다이의 제1표면이 인터포우저의 제1표면을 상반되게 하고, 상기 다수의 본딩 패드가 상기 다수의 바이어스에 전기적으로 연결되도록 반도체 다이를 인터포우저에 부착시키며; 상기 다수의 바이어스를 기판에 전기적으로 연결하는 수단을 제공하는 단계를 구비하는 복합 플립 칩 반도체 소자를 제조하는 방법.
  3. 복합 플립 칩 반도체 소자의 번-인을 강화시키는 처리 방법에 있어서, 다수의 다이를 받아들이는 영역(22)과 제1 및 제2표면을 가지며, 제1표면이 제1표면으로부터 제2표면으로 확장하는 다수의 전기적 바이어스(24)에 전기적으로 연결된 다수의 도전 트레이스(26)를 가지는 인터포우저 기판 재료(60)를 제공하며; 반도체 다이가 상기 다수의 바이어스에 전기적으로 연결되도록 반도체 다이(12)를 다이를 받아들이는 영역 각각에 위치시키고; 인터포우저 기판 재료가 소정의 응력을 받게 함으로써, 반도체 다이 각각을 번-인하며; 다이를 받아들이는 영역들을 분리하여, 다수의 복합 플립 칩 반도체 소자(10)를 형성하도록 인터포우저 기판 재료를 개별화하는 단계를 구비하는 복합 플립 칩 반도체 소자의 번-인을 강화시키는 처리 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019920010970A 1991-03-27 1992-06-24 복합 플립 칩 반도체 소자와 그 제조 및 번-인(burning-in) 방법 KR930001365A (ko)

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Application Number Priority Date Filing Date Title
US722,429 1991-03-27
US72242991A 1991-06-27 1991-06-27
US72244991A 1991-06-27 1991-06-27
US722,449 1991-06-27

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