KR920014047A - Data access circuits - Google Patents

Data access circuits Download PDF

Info

Publication number
KR920014047A
KR920014047A KR1019900022784A KR900022784A KR920014047A KR 920014047 A KR920014047 A KR 920014047A KR 1019900022784 A KR1019900022784 A KR 1019900022784A KR 900022784 A KR900022784 A KR 900022784A KR 920014047 A KR920014047 A KR 920014047A
Authority
KR
South Korea
Prior art keywords
data
control
buffer means
cpu
address
Prior art date
Application number
KR1019900022784A
Other languages
Korean (ko)
Other versions
KR930010283B1 (en
Inventor
홍재환
송광석
Original Assignee
경상현
재단법인 한국전자통신연구소
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 경상현, 재단법인 한국전자통신연구소 filed Critical 경상현
Priority to KR1019900022784A priority Critical patent/KR930010283B1/en
Publication of KR920014047A publication Critical patent/KR920014047A/en
Application granted granted Critical
Publication of KR930010283B1 publication Critical patent/KR930010283B1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/22—Arrangements for supervision, monitoring or testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Information Transfer Systems (AREA)

Abstract

내용 없음No content

Description

데이터 액세스 회로Data access circuits

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 일실시예 구성을 나타낸 블럭도.2 is a block diagram showing an embodiment configuration of the present invention.

Claims (1)

CPU의 데이터 액세스 속도 향상을 위한 데이터 액세스 회로에 있어서, 시스팀 버스에 연결되어 CPU가 데이터 및 어드레스를 라이트(write)할때 제어 신호에 의해 동기가 되었을때 리시드 단자를 열어 주는 기능을 하며 쌍방향 버스 트랜시버로 구성된 데이터 및 어드레스 버퍼 수단(20); 상기 데이터 및 어드레스 버퍼 수단(20)가 시스팀 버스에 연결되어 상기 데이터 및 어드레스 버퍼 수단(20)에 제어 신호를 제공하는 제어 버퍼 및 제어 수단(30); 상기 데이터 및 어드레스 버퍼 수단(20)에 연결되어 CPU가 데이터 액세스 종료 신호를 받음과 동시에 한 사이클 수행을 완료할 수 있도록 데이터 종료 신호를 미리 보내고, 내부적으로 CPU의 어드레스 스토로브(AS) 신호가 없어도 정확한 데이터를 라이트할 수 있도록 지속적인 다른 하나의 어드레스 스토로브(AS) 신호를 만드는 데이터 래치 버퍼 수단(50); 상기 데이터 래치 버퍼 수단(50)과 상기 제어 버퍼 및 제어 수단(30)에 연결되어 데이터 래치 버퍼 수단(50)의 제어 신호를 제공하여 정확한 데이터를 라이트할 수 있도록 하며 래치 버퍼 제어 수단(60); 및 상기 데이터 및 어드레스 버퍼 수단(20)과 데이터 래치 버퍼수단(50)에 연결된 메모리 어레이 수단(40)으로 구성된 것을 특징으로 하는 데이터 액세스 회로.A data access circuit for improving the data access speed of a CPU, which is connected to a system bus and opens a terminal when the CPU is synchronized by a control signal when the CPU writes data and addresses. Data and address buffer means 20 comprised of a transceiver; Control buffer and control means (30) for connecting said data and address buffer means (20) to a system bus to provide control signals to said data and address buffer means (20); It is connected to the data and address buffer means 20 and sends a data end signal in advance so that the CPU can receive a data access end signal and complete one cycle, and there is no internally the address stove signal of the CPU. Data latch buffer means 50 for generating another continuous address stove (AS) signal so that the correct data can be written; A latch buffer control means (60) connected to the data latch buffer means (50) and the control buffer and the control means (30) to provide a control signal of the data latch buffer means (50) to write correct data; And memory array means (40) coupled to said data and address buffer means (20) and data latch buffer means (50). ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900022784A 1990-12-31 1990-12-31 Data access circuit KR930010283B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900022784A KR930010283B1 (en) 1990-12-31 1990-12-31 Data access circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900022784A KR930010283B1 (en) 1990-12-31 1990-12-31 Data access circuit

Publications (2)

Publication Number Publication Date
KR920014047A true KR920014047A (en) 1992-07-30
KR930010283B1 KR930010283B1 (en) 1993-10-16

Family

ID=19309200

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900022784A KR930010283B1 (en) 1990-12-31 1990-12-31 Data access circuit

Country Status (1)

Country Link
KR (1) KR930010283B1 (en)

Also Published As

Publication number Publication date
KR930010283B1 (en) 1993-10-16

Similar Documents

Publication Publication Date Title
KR890008691A (en) Data processor devices
KR920004946A (en) VGA input / output port access circuit
KR920014047A (en) Data access circuits
KR910010340A (en) Expansion addressing circuit and adapter card
KR930001217A (en) Semiconductor memory
KR880008177A (en) Control circuit of local area network
KR940017592A (en) Light Latch Control Device of Memory Board
KR970016898A (en) Data processor and access method
KR910001566A (en) Common Memory Access
KR920022110A (en) PC Interrupt System
KR920018587A (en) Circuitry for Interfacing Graphics System Processors and Memory in VME Systems
KR940015752A (en) 64-bit to 32-bit data bus interface unit
KR930010727A (en) DMA address expansion unit of computer system
KR940022285A (en) Data processing system and processor used in it
KR890010686A (en) Improved Data Processing Speed of Microprocessor
KR910012928A (en) Computer memory expansion system
KR970049590A (en) Memory read and write control device
KR950024080A (en) Cache Data Transmitter in Multiprocessor System
KR910008724A (en) Fast access device in cashew memory
KR960025066A (en) Dual port memory system using commercial DRAM
KR910017291A (en) Old Data Processing Circuit
KR890005611A (en) How to address memory using a data bus
KR960035219A (en) Input Port Expansion Circuit in Digital Signal Processing (DSP) Chip
KR950033839A (en) Address blocking circuit
KR910020588A (en) Image and Graphic Overlap Circuit

Legal Events

Date Code Title Description
A201 Request for examination
N231 Notification of change of applicant
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070919

Year of fee payment: 15

LAPS Lapse due to unpaid annual fee