KR890010686A - Improved Data Processing Speed of Microprocessor - Google Patents

Improved Data Processing Speed of Microprocessor Download PDF

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Publication number
KR890010686A
KR890010686A KR870014218A KR870014218A KR890010686A KR 890010686 A KR890010686 A KR 890010686A KR 870014218 A KR870014218 A KR 870014218A KR 870014218 A KR870014218 A KR 870014218A KR 890010686 A KR890010686 A KR 890010686A
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KR
South Korea
Prior art keywords
rom
data
output
ram
signal
Prior art date
Application number
KR870014218A
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Korean (ko)
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KR900005452B1 (en
Inventor
윤영희
이경섭
Original Assignee
안시환
삼성전자 주식회사
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Priority to KR1019870014218A priority Critical patent/KR900005452B1/en
Publication of KR890010686A publication Critical patent/KR890010686A/en
Application granted granted Critical
Publication of KR900005452B1 publication Critical patent/KR900005452B1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Stored Programmes (AREA)
  • Microcomputers (AREA)

Abstract

내용 없음No content

Description

마이크로 프로세서의 데이터 처리속도를 개선한 회로Circuit improves data processing speed of microprocessor

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

첨부된 도면은 본 발명의 회로도이다.The accompanying drawings are circuit diagrams of the invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

G1-G6: 논리게이트 FF : 플립플롭G 1 -G 6 : Logic Gate FF: Flip-Flop

MM : 단안정멀티바이브레이터 CTR : 카운터MM: Monostable Multivibrator CTR: Counter

ROM : 롬 RAM : 램ROM: ROM RAM: RAM

BF1, BF2: 버퍼BF 1 , BF 2 : Buffer

Claims (1)

롬에 저장되어 있는 시스템 프로그램을 마이크로프로세서가 액세스하여 데이터 처리하는 데이터 시스템에 있어서, 시스템의 초기전원공급시에 리세트신호에 의해 클리어되어 정상출력을 반전시켜 마이크로프로세서가 동작되지 않게하는 플립플롭 FF과, 시스템의 클럭을 리세트신호에 의해 분주하여 출력하는 분주회로 FD와, 상기 분주회로 FD의 출력으로 동기되고 클리어된 플립플롭 FF의 로우레벨출력신호로 인에이블되어 계수동작을 하는 카운터 CTR과, 시스템의 클럭신호를 입력할 때 단안정멀티바이브레이터 MM에서 출력되는 발진신호가 반전게이트 G4를 통해 입력되어 인에이블되고, 상기 플립플롭의 로우레벨 신호로 칩인에이블되어서 카운터의 출력신호에 의해 지정된 어드레스에 대응하는 데이터를 출력하는 롬 ROM과, 상기 반전게이트 G4의 출력과 시스템의 데이터기입신호를 입력하는 앤드게이트 G5의 출력으로 제어되고, 상기 플립플롭의 로우레벨신호를 입력하는 앤드게이트 G6의 출력으로 인에이블되어서 카운터의 출력에 의해 지정된 어드레스에 롬 ROM의 독출데이터가 기입되는 램 RAM과, 시스템의 데이터버스와 접속되어서 시스템에서 상기 롬 ROM과 램 RAM과의 데이터전송을 제어하는 버퍼 BF1과 시스템의 어드레스버스와 접속되어서 시스템에서 상기 롬 ROM과 램 RAM으로 데이터전송을 제어하는 버퍼 BF, 롬의 데이터가 램에 모두 기입될 때 카운터 CTR에서 출력되는 제어신호가 클리어상태의 플립플롭의 출력을 반전시켜서 마이크로프로세서에서 램 RAM의 데이터를 액세스하여 처리할 수 있도록 상기 버퍼 BF1과 BF2의 인에이블단자에 제공하도록 연결한 것을 특징으로 하는 마이크로프로세서의 데이터처리 속도를 개선한 회로.In a data system in which a microprocessor accesses a system program stored in a ROM and processes data, a flip-flop FF is cleared by a reset signal at the initial power supply of the system and inverts the normal output so that the microprocessor is not operated. A division circuit FD for dividing and outputting the clock of the system by a reset signal; a counter CTR enabled with a low level output signal of the flip-flop FF cleared and synchronized with the output of the division circuit FD; When the clock signal of the system is input, the oscillation signal output from the monostable multivibrator MM is input through the inverting gate G 4 and is enabled. The chip is enabled by the low level signal of the flip-flop to be designated by the output signal of the counter. ROM for outputting the data corresponding to the ROM address and, in the inverting gate G 4 A data write signal and the force system Is controlled by the output of the AND gate G 5 which inputs, and is enabled by the output of the AND gate G 6 which inputs the low level signal of the flip-flop, and the read data of the ROM ROM is written to the address designated by the output of the counter. A buffer BF 1 connected to a RAM and a data bus of a system to control data transfer between the ROM ROM and a RAM RAM in the system and a data bus to a ROM ROM and RAM RAM from the system connected to an address bus of the system. buffer BF, and the buffer BF 1 ROM of that data can time the writing to both the RAM by the control signal outputted from the counter CTR inverts the output of the clear state the flip-flop to be processed by accessing the data in the RAM RAM in microprocessor the data processing speed of the microprocessor, characterized in that connection to provide the enable terminal of the BF 2 gae A circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019870014218A 1987-12-12 1987-12-12 Speed - up circuit for micro precessor KR900005452B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019870014218A KR900005452B1 (en) 1987-12-12 1987-12-12 Speed - up circuit for micro precessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019870014218A KR900005452B1 (en) 1987-12-12 1987-12-12 Speed - up circuit for micro precessor

Publications (2)

Publication Number Publication Date
KR890010686A true KR890010686A (en) 1989-08-10
KR900005452B1 KR900005452B1 (en) 1990-07-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019870014218A KR900005452B1 (en) 1987-12-12 1987-12-12 Speed - up circuit for micro precessor

Country Status (1)

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KR (1) KR900005452B1 (en)

Also Published As

Publication number Publication date
KR900005452B1 (en) 1990-07-30

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