KR920018587A - Circuitry for Interfacing Graphics System Processors and Memory in VME Systems - Google Patents

Circuitry for Interfacing Graphics System Processors and Memory in VME Systems Download PDF

Info

Publication number
KR920018587A
KR920018587A KR1019910004710A KR910004710A KR920018587A KR 920018587 A KR920018587 A KR 920018587A KR 1019910004710 A KR1019910004710 A KR 1019910004710A KR 910004710 A KR910004710 A KR 910004710A KR 920018587 A KR920018587 A KR 920018587A
Authority
KR
South Korea
Prior art keywords
graphics system
vme
signal
bus
circuitry
Prior art date
Application number
KR1019910004710A
Other languages
Korean (ko)
Other versions
KR930003446B1 (en
Inventor
박영규
Original Assignee
안시환
삼성항공산업 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 안시환, 삼성항공산업 주식회사 filed Critical 안시환
Priority to KR1019910004710A priority Critical patent/KR930003446B1/en
Publication of KR920018587A publication Critical patent/KR920018587A/en
Application granted granted Critical
Publication of KR930003446B1 publication Critical patent/KR930003446B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)

Abstract

내용 없음No content

Description

VME 시스템에 있어 그래픽 시스템 프로세서와 기억장치와의 인터페이싱을 위한 회로Circuitry for Interfacing Graphics System Processors and Memory in VME Systems

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 의한 회로 구성도.2 is a circuit configuration diagram according to the present invention.

Claims (1)

VME(Versa Module European)시스템에 있어 그래픽 시스템 프로세서(GSP)와 기억장치인 DRAM과의 인터페이싱 장치에 있어서, 상기한 그래픽 시스템 프로세서(GSP)의 로컬 어드레스/데이타 버스로 부터의 신호(LAD0~LAD7)를 각각 공급받는 3상태 출력을 갖는 제1 및 제2의 버스 트랜시버⑴, ⑵와, 또 다른 로컬 에드레스/데이타 버스의 신호(LAD8이상)를 받는 버퍼/라인 드라이버⑶를 포함하며, 컬럼 어드레스 생성을 위한 COLS＊신호는 상기 제1의 버스 트랜시버⑴ 및 버퍼/라인드라이버⑶의 인에이블 단자에 연결되고, 상기 COLS＊신호의 역은 로우 어드레스 생성을 위해 제2의 버스 트랜시버⑵의 인에이블 단자에 연결되며, 상기한 구성 소자들의 출력을 억세스를 위한 어드레스를 구성함을 특징으로 하는 VME 시스템에 있어 그래픽 시스템 프로세서와 기억장치와의 인터페이싱을 위한 회로.In an interfacing device between a graphics system processor (GSP) and a DRAM, which is a storage device, in a Versa Module European (VME) system, a signal from the local address / data bus of the graphics system processor (GSP) (LAD0 to LAD7). First and second bus transceivers, each having a tri-state output supplied with V, and a buffer / line driver for receiving signals from another local address / data bus (LAD8 or higher), generating column addresses. The COLS * signal for is coupled to the enable terminal of the first bus transceiver and the buffer / line driver, and the inverse of the COLS * signal is connected to the enable terminal of the second bus transceiver for row address generation. And an interface between the graphics system processor and the storage device in the VME system, characterized in that an address for accessing the outputs of the components is configured. Circuit for Singh. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910004710A 1991-03-25 1991-03-25 Interfacing circuit between graphic system processor and memory KR930003446B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004710A KR930003446B1 (en) 1991-03-25 1991-03-25 Interfacing circuit between graphic system processor and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004710A KR930003446B1 (en) 1991-03-25 1991-03-25 Interfacing circuit between graphic system processor and memory

Publications (2)

Publication Number Publication Date
KR920018587A true KR920018587A (en) 1992-10-22
KR930003446B1 KR930003446B1 (en) 1993-04-29

Family

ID=19312497

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004710A KR930003446B1 (en) 1991-03-25 1991-03-25 Interfacing circuit between graphic system processor and memory

Country Status (1)

Country Link
KR (1) KR930003446B1 (en)

Also Published As

Publication number Publication date
KR930003446B1 (en) 1993-04-29

Similar Documents

Publication Publication Date Title
US6233650B1 (en) Using FET switches for large memory arrays
KR920704222A (en) High-Speed, Flexible Source / Destination Data Burst Direct Memory Access Controller
KR850006652A (en) Integrated circuits with embedded processes and memory and systems using them
EP0395559A3 (en) Distributed cache dram chip
KR930023841A (en) Multibus architecture
KR890007173A (en) Address bus controller
KR970062925A (en) Low power data processing system and method for interfacing with external device
KR950012245A (en) Single Chip Microcomputer with User Designed Circuit
KR920018587A (en) Circuitry for Interfacing Graphics System Processors and Memory in VME Systems
JP2531503B2 (en) Semiconductor assembly
JPH04332067A (en) System for controlling communication between computer processor and plurality of peripheral devices
TW372292B (en) A method and memory controller for accessing a memory and a computer system
Downing et al. The FASTBUS segment interconnect
KR920014047A (en) Data access circuits
KR950020205A (en) Buffer RAM Controller for Dual Port Support and VME Interface
KR940007685A (en) Integrated circuit data processor and data processing device using the same
KR910008724A (en) Fast access device in cashew memory
KR940022285A (en) Data processing system and processor used in it
KR930004862A (en) Redundant interface device using dual port memory
KR970016898A (en) Data processor and access method
KR100248339B1 (en) The interface circuit for memory system.
KR910012874A (en) Snoop Interface Subunit
KR920006860A (en) Multi-Process System Arbiter Delay Circuit
KR940000990A (en) Multiprocessor System with Bus Handler
KR950023121A (en) Matching circuit for controlling external devices of the electronic exchange subprocessor

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970829

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee