KR920022110A - PC Interrupt System - Google Patents

PC Interrupt System Download PDF

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Publication number
KR920022110A
KR920022110A KR1019910009036A KR910009036A KR920022110A KR 920022110 A KR920022110 A KR 920022110A KR 1019910009036 A KR1019910009036 A KR 1019910009036A KR 910009036 A KR910009036 A KR 910009036A KR 920022110 A KR920022110 A KR 920022110A
Authority
KR
South Korea
Prior art keywords
logic
interrupt system
memory
buffer
slot
Prior art date
Application number
KR1019910009036A
Other languages
Korean (ko)
Other versions
KR940001271B1 (en
Inventor
이원택
김창일
Original Assignee
박성규
대우통신 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박성규, 대우통신 주식회사 filed Critical 박성규
Priority to KR1019910009036A priority Critical patent/KR940001271B1/en
Publication of KR920022110A publication Critical patent/KR920022110A/en
Application granted granted Critical
Publication of KR940001271B1 publication Critical patent/KR940001271B1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24Handling requests for interconnection or transfer for access to input/output bus using interrupt

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Bus Control (AREA)

Abstract

내용 없음No content

Description

PC용 인터럽트 시스템PC Interrupt System

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 전체적인 구성을 보인 구성도.1 is a block diagram showing the overall configuration of the present invention.

제2도는 본 발명의 리드 파트(read part)를 보인 구성도.Figure 2 is a block diagram showing a lead part (read part) of the present invention.

제3도는 본 발명이 라이트 파트(write part)를 보인 구성도.3 is a block diagram showing a write part of the present invention.

Claims (1)

PC의 슬롯(1)에 설치된 인터럽트 라인(2)과 래치 로직(3) 및 버퍼/메모리 로직(4)(4')를 접속하고, PC의 슬롯(1)에 설치된 I/O 및 메모리 어드레스 그리고 콘트롤 신호 단자(다)(라)를 디코딩 로직(5)에 연결하며 디코딩 어드레스와 콘트롤 시그널 그리고 데이타 버스를 버퍼/메모리 로직(4)(4')에 연결하여서 됨을 특징으로 하는 PC용 인터럽트 시스템.The interrupt line 2 installed in the slot 1 of the PC, the latch logic 3 and the buffer / memory logic 4, 4 'are connected, and the I / O and memory addresses installed in the slot 1 of the PC An interrupt system for a PC characterized by connecting a control signal terminal (c) to a decoding logic (5) and a decoding address, a control signal and a data bus to a buffer / memory logic (4) (4 '). ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019910009036A 1991-05-31 1991-05-31 Interrupt system for personal computer KR940001271B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910009036A KR940001271B1 (en) 1991-05-31 1991-05-31 Interrupt system for personal computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910009036A KR940001271B1 (en) 1991-05-31 1991-05-31 Interrupt system for personal computer

Publications (2)

Publication Number Publication Date
KR920022110A true KR920022110A (en) 1992-12-19
KR940001271B1 KR940001271B1 (en) 1994-02-18

Family

ID=19315269

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910009036A KR940001271B1 (en) 1991-05-31 1991-05-31 Interrupt system for personal computer

Country Status (1)

Country Link
KR (1) KR940001271B1 (en)

Also Published As

Publication number Publication date
KR940001271B1 (en) 1994-02-18

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