KR920010759A - 저 저항 접점을 제조하는 방법 - Google Patents
저 저항 접점을 제조하는 방법 Download PDFInfo
- Publication number
- KR920010759A KR920010759A KR1019910018403A KR910018403A KR920010759A KR 920010759 A KR920010759 A KR 920010759A KR 1019910018403 A KR1019910018403 A KR 1019910018403A KR 910018403 A KR910018403 A KR 910018403A KR 920010759 A KR920010759 A KR 920010759A
- Authority
- KR
- South Korea
- Prior art keywords
- layer
- metal silicide
- integrated circuit
- insulating layer
- silicide
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 claims description 20
- 239000010410 layer Substances 0.000 claims 30
- 229910021332 silicide Inorganic materials 0.000 claims 20
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims 20
- 229910052751 metal Inorganic materials 0.000 claims 17
- 239000002184 metal Substances 0.000 claims 17
- 239000012790 adhesive layer Substances 0.000 claims 8
- 229910004298 SiO 2 Inorganic materials 0.000 claims 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 3
- 229920005591 polysilicon Polymers 0.000 claims 3
- 229910052715 tantalum Inorganic materials 0.000 claims 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical group [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims 3
- 239000010936 titanium Substances 0.000 claims 3
- 229910052719 titanium Inorganic materials 0.000 claims 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical group [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims 3
- 229910021342 tungsten silicide Inorganic materials 0.000 claims 3
- 238000005530 etching Methods 0.000 claims 2
- 238000005229 chemical vapour deposition Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제3도는 본 발명에 따른 바람직한 공정도임.
Claims (29)
- 접착층과 절연층을 관통하여 접점 개방부를 형성시키고, 또 집적 회로의 표면에 금속 규화물 내부 접속층을 형성시키는 단계를 포함하는, 집적회로내의 저 저항 접점을 제조하는 방법.
- 제1항에 있어서, 접착층이 폴리실리콘인 방법.
- 제1항에 있어서, 절연층이 SiO2인 방법.
- 제1항에 있어서, 금속 규화물 내부 접속층이 집적회로 상에 증착된 방법.
- 제1항에 있어서, 금속 규화물 내부 접속층이 규화 텅스텐인 방법.
- 제1항에 있어서, 금속 규화물 내부 접속층이 규화 탄탈륨인 방법.
- 제1항에 있어서, 금속 규화물 내부 접속층이 형성되기 전에 산화물 용해 필름이 집적회로상에 형성되는 방법.
- 제1항에 있어서, 산화물 용해 필름이 티탄인 방법.
- 제1항에 있어서, 산화물 용해 필름이 질화 티탄인 방법.
- 집적회로상에 절연층을 형성시키고, 절연층상에 접착층을 형성시키고, 접착층과 절연층을 에칭하여 집적회로의 소정 부분을 노출시키는 접점 개방부를 형성시키고, 집적회로 상에 금속 규화물층을 형성시키며, 또 금속 규화물층과 접촉층을 에칭하여 내부 접속구조를 형성시키는 단계를 포함하는, 집적회로내에 저 저항 접점을 제조하는 방법.
- 제10항에 있어서, 절연층이 SiO2인 방법.
- 제10항에 있어서, 접착층이 폴리실리콘인 방법.
- 제10항에 있어서, 금속 규화물이 집적회로 상에 스퍼터링되는 방법.
- 제10항에 있어서, 금속 규화물층이 화학적 증기 증착에 의해 증착되는 방법.
- 제14항에 있어서, 금속 규화물 규화 텅스텐인 방법.
- 제13항에 있어서, 금속 규화물층이 규화 탄탈륨인 방법.
- 제10항에 있어서, 금속 규화물층이 형성되기 전에 산화물 용해 필름이 집적회로 상에 형성되는 방법.
- 제17항에 있어서, 산화물 용해 필름이 집적 회로상에 증착되는 방법.
- 제17항에 있어서, 산화물 용해 필름이 증착된 후 어닐링되는 방법.
- 제17항에 있어서, 산화물 용해 필름이 티탄인 방법.
- 제17항에 있어서, 산화물 용해 필름이 질화 티탄인 방법.
- 도전층, 도전층 위의 절연층, 절연층 위의 접착층, 도전층의 소정 영역을 노출시키는 접착층과 절연층을 관통하는 접점 개방부, 및 접점 개방부내 및 접착층의 소정 영역상에 금속 규화물층을 포함하는 전기 접점장치.
- 제22항에 있어서, 절연층이 SiO2인 장치.
- 제22항에 있어서, 접착층이 폴리실리콘인 장치.
- 제22항에 있어서, 금속 규화물층이 규화 텅스텐인 장치.
- 제22항에 있어서, 금속 규화물층이 규화 탄탈륨인 장치.
- 제22항에 있어서, 금속 규화물층과 노출된 도전층 영역 사이에 위치하는 산화물 용해 필름을 더 포함하는 장치.
- 제27항에 있어서, 산화물 용해 필름이 티탄인 장치.
- 제27항에 있어서, 산화물 용해 필름이 질화 티탄인 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US61463590A | 1990-11-16 | 1990-11-16 | |
US07/614,635 | 1990-11-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR920010759A true KR920010759A (ko) | 1992-06-27 |
Family
ID=24462108
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019910018403A KR920010759A (ko) | 1990-11-16 | 1991-10-18 | 저 저항 접점을 제조하는 방법 |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0486244A1 (ko) |
JP (1) | JPH04286324A (ko) |
KR (1) | KR920010759A (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2761528B1 (fr) * | 1997-03-26 | 2000-01-28 | Sgs Thomson Microelectronics | Procede de depot de metallisation |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0618213B2 (ja) * | 1982-06-25 | 1994-03-09 | 松下電子工業株式会社 | 半導体装置の製造方法 |
US4519126A (en) * | 1983-12-12 | 1985-05-28 | Rca Corporation | Method of fabricating high speed CMOS devices |
JPH0719841B2 (ja) * | 1987-10-02 | 1995-03-06 | 株式会社東芝 | 半導体装置 |
KR930004295B1 (ko) * | 1988-12-24 | 1993-05-22 | 삼성전자 주식회사 | Vlsi 장치의 n+ 및 p+ 저항영역에 저저항 접속방법 |
EP0388563B1 (en) * | 1989-03-24 | 1994-12-14 | STMicroelectronics, Inc. | Method for forming a contact/VIA |
-
1991
- 1991-10-18 KR KR1019910018403A patent/KR920010759A/ko not_active Application Discontinuation
- 1991-11-11 EP EP91310398A patent/EP0486244A1/en not_active Withdrawn
- 1991-11-14 JP JP3299130A patent/JPH04286324A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
JPH04286324A (ja) | 1992-10-12 |
EP0486244A1 (en) | 1992-05-20 |
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