KR940010214A - 반도체 소자의 금속콘택 형성방법 - Google Patents

반도체 소자의 금속콘택 형성방법 Download PDF

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Publication number
KR940010214A
KR940010214A KR1019920019287A KR920019287A KR940010214A KR 940010214 A KR940010214 A KR 940010214A KR 1019920019287 A KR1019920019287 A KR 1019920019287A KR 920019287 A KR920019287 A KR 920019287A KR 940010214 A KR940010214 A KR 940010214A
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South Korea
Prior art keywords
thin film
film
metal
double
contact
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KR1019920019287A
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English (en)
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KR950010858B1 (ko
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최경근
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김주용
현대전자산업 주식회사
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Priority to KR1019920019287A priority Critical patent/KR950010858B1/ko
Priority to US08/138,694 priority patent/US5380680A/en
Priority to JP5260772A priority patent/JPH0770595B2/ja
Publication of KR940010214A publication Critical patent/KR940010214A/ko
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H01L21/32053—Deposition of metallic or metal-silicide layers of metal-silicide layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/97—Specified etch stop material

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 금속 배선의 신뢰성을 향상시키는 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거 방법에 관한 것으로, 반도체 기판(1)에 형성된 필드 산화막(2), 층간 절연을 위한 절연막(4), 상기 절연막(4) 사이에 형성되어 있는 폴리실리콘막(3)이 형성되어 있는 반도체 소자의 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거 방법에 있어서, 상기 반도체 기판(1)과의 금속 배선을 이루기 위하여 제1콘택홀을 형성하고 텅스텐(5)을 상기 제1콘택 층을 메우는 제1단계, 상기 제1단계후에 이중 박막(6,7)을 증착 하는 제2단계, 상기 제2단계 후에 제2콘택홀을 형성하기 위하여 상기 이중 박막(6,7)의 상부층 박막(7) 상부에 감광막(8)을 도포하여 패턴하고 이중박막의 상부층 박막(7)과 하부층 박막(6)을 차례로 식각하여 제2콘택홀을 형성하는 제3단계, 상기 제3단계 후의 감광막(8)을 제거하고 상층 박막(7)을 식각하고 Al합금(9)를 증착하는 제4단계를 구비하여 이루어 지는 것을 특징으로 하는 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거 방법에 관한 것이다.

Description

반도체 소자의 금속콘택 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제4도는 본 발명에 따른 금속배선 형성 공정도.

Claims (3)

  1. 반도체 기판(1)에 형성된 필드 산화막(2), 층간 절연을 위한 절연막(4), 상기 절연막(4)사이에 형성되어 있는 폴리실리콘막(3)이 형성되어 있는 반도체 소자의 콘택 플러그 금속과 금속선 사이의 감광막 잔여를 제거방법에 있어서, 상기 반도체 기판(1)과의 금속 배선을 이루기 위하여 제1콘택홀을 형성하고 텅스텐(5)으로 상기 제1콘택홀을 메우는 제1단계, 상기 제1단계 후에 이중 박막(6,7)을 증착하는 제2단계, 상기 제2단계 후에 제2콘택홀을 형성하기 위하여 상기 이중 박막(6,7)의 상부를 박막(7)상부에 감광막(8)을 도포 하여 패턴하고 이중박막의 상부층 박막(7)과 하부층 박막(6)을 차례로 식각하여 제2콘택홀을 형성하는 제3단계, 상기 제3단계 후에 감광막(8)을 제거하고 상측 박막(7)을 식각하고 Al합금(9)를 증착하는 제4단계를 포함하여 이루어 지는 것을 특징으로 하는 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거 방법.
  2. 제1항에 있어서, 상기 제2단계의 이중막은 하부층에 TiCl4, SiH4반응기체를 이용하여 화학기상 증착법으로 300 내지 500℃에서 900 내지 1000Å 두께로 증착된 TISi2(6) 박막이고, 상부층은 스퍼터링 방법으로 100 내지 1000Å 두께로 증착된 TiN(7)박막인 것을 특징으로 하는 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거방법.
  3. 제1항에 있어서, 상기 4단계의 상부층 박막(7)의 식각 용액은 NH2OH용액인 것을 특징으로 하는 콘택 플러그 금속과 금속선 사이의 감광막 잔여물 제거 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920019287A 1992-10-20 1992-10-20 반도체 소자의 금속콘택 형성방법 KR950010858B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920019287A KR950010858B1 (ko) 1992-10-20 1992-10-20 반도체 소자의 금속콘택 형성방법
US08/138,694 US5380680A (en) 1992-10-20 1993-10-19 Method for forming a metal contact of a semiconductor device
JP5260772A JPH0770595B2 (ja) 1992-10-20 1993-10-19 半導体素子の金属コンタクト形成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920019287A KR950010858B1 (ko) 1992-10-20 1992-10-20 반도체 소자의 금속콘택 형성방법

Publications (2)

Publication Number Publication Date
KR940010214A true KR940010214A (ko) 1994-05-24
KR950010858B1 KR950010858B1 (ko) 1995-09-25

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US (1) US5380680A (ko)
JP (1) JPH0770595B2 (ko)
KR (1) KR950010858B1 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07130852A (ja) * 1993-11-02 1995-05-19 Sony Corp 金属配線材料の形成方法
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
JPH09205185A (ja) 1996-01-26 1997-08-05 Mitsubishi Electric Corp 半導体装置および半導体装置の製造方法
DE19629736C2 (de) * 1996-01-26 2000-12-14 Mitsubishi Electric Corp Halbleitereinrichtung mit selbstjustierendem Kontakt und Herstellungsverfahren dafür
DE19655075C2 (de) * 1996-01-26 2003-04-03 Mitsubishi Electric Corp Halbleitereinrichtung mit Kontaktlöchern und Herstellungsverfahren einer Halbleitereinrichtung
JP3631380B2 (ja) * 1998-08-28 2005-03-23 株式会社東芝 半導体装置及びその製造方法
TW413844B (en) * 1998-11-26 2000-12-01 Samsung Electronics Co Ltd Manufacturing methods of thin film transistor array panels for liquid crystal displays and photolithography method of thin films
TW413949B (en) * 1998-12-12 2000-12-01 Samsung Electronics Co Ltd Thin film transistor array panels for liquid crystal displays and methods of manufacturing the same
US9196583B1 (en) * 2014-05-09 2015-11-24 Qualcomm Incorporated Via material selection and processing
US9305785B2 (en) 2014-06-30 2016-04-05 Globalfoundries Inc. Semiconductor contacts and methods of fabrication
KR102556023B1 (ko) * 2016-02-26 2023-07-17 삼성디스플레이 주식회사 감광성 박막 소자 및 이를 포함하는 생체 정보 감지 장치

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Publication number Priority date Publication date Assignee Title
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US5026666A (en) * 1989-12-28 1991-06-25 At&T Bell Laboratories Method of making integrated circuits having a planarized dielectric
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten
JP3123092B2 (ja) * 1991-03-06 2001-01-09 日本電気株式会社 半導体装置の製造方法
US5219793A (en) * 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
US5204286A (en) * 1991-10-15 1993-04-20 Micron Technology, Inc. Method of making self-aligned contacts and vertical interconnects to integrated circuits
US5223084A (en) * 1991-11-25 1993-06-29 Hewlett-Packard Company Simultaneous dielectric planarization and contact hole etching

Also Published As

Publication number Publication date
JPH0770595B2 (ja) 1995-07-31
KR950010858B1 (ko) 1995-09-25
JPH06283613A (ja) 1994-10-07
US5380680A (en) 1995-01-10

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