KR890016569A - 반도체 기억장치 - Google Patents

반도체 기억장치

Info

Publication number
KR890016569A
KR890016569A KR1019890005087A KR890005087A KR890016569A KR 890016569 A KR890016569 A KR 890016569A KR 1019890005087 A KR1019890005087 A KR 1019890005087A KR 890005087 A KR890005087 A KR 890005087A KR 890016569 A KR890016569 A KR 890016569A
Authority
KR
South Korea
Prior art keywords
semiconductor memory
semiconductor
memory
Prior art date
Application number
KR1019890005087A
Other languages
English (en)
Other versions
KR950007834B1 (ko
Inventor
유키히토 오와키
Original Assignee
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시키가이샤 도시바 filed Critical 가부시키가이샤 도시바
Publication of KR890016569A publication Critical patent/KR890016569A/ko
Application granted granted Critical
Publication of KR950007834B1 publication Critical patent/KR950007834B1/ko

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1019890005087A 1988-04-18 1989-04-18 반도체 기억장치 KR950007834B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63093511A JP2895488B2 (ja) 1988-04-18 1988-04-18 半導体記憶装置及び半導体記憶システム
JP63-93511 1988-04-18

Publications (2)

Publication Number Publication Date
KR890016569A true KR890016569A (ko) 1989-11-29
KR950007834B1 KR950007834B1 (ko) 1995-07-20

Family

ID=14084374

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890005087A KR950007834B1 (ko) 1988-04-18 1989-04-18 반도체 기억장치

Country Status (4)

Country Link
US (5) US5497351A (ko)
JP (1) JP2895488B2 (ko)
KR (1) KR950007834B1 (ko)
DE (1) DE3912695C2 (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2895488B2 (ja) * 1988-04-18 1999-05-24 株式会社東芝 半導体記憶装置及び半導体記憶システム
DE4039934A1 (de) * 1990-12-14 1992-06-17 Gutehoffnungshuette Man Einrichtung zum zerquetschen von zusammenbackenden materialien am austrag eines bunkers bzw. an einer foerderbanduebergabestelle
JP3179788B2 (ja) * 1991-01-17 2001-06-25 三菱電機株式会社 半導体記憶装置
JPH0536271A (ja) * 1991-07-30 1993-02-12 Nec Corp 半導体メモリ
JPH0713859A (ja) * 1993-06-25 1995-01-17 Mitsubishi Electric Corp 半導体記憶素子用コントローラ
US5787267A (en) * 1995-06-07 1998-07-28 Monolithic System Technology, Inc. Caching method and circuit for a memory system with circuit module architecture
US5914899A (en) * 1995-07-05 1999-06-22 Kabushiki Kaisha Toshiba Semiconductor memory having a page mode in which previous data in an output circuit is reset before new data is supplied
US5654932A (en) * 1995-10-04 1997-08-05 Cirrus Logic, Inc. Memory devices with selectable access type and methods using the same
JPH10162580A (ja) * 1996-11-29 1998-06-19 Mitsubishi Electric Corp スタティック型半導体記憶装置とその動作方法
JPH10283770A (ja) * 1997-04-07 1998-10-23 Oki Electric Ind Co Ltd 半導体メモリ装置およびその読み出しおよび書き込み方法
KR100295641B1 (ko) * 1998-01-23 2001-08-07 김영환 글로벌워드라인드라이버
US6130843A (en) 1998-09-02 2000-10-10 Micron Technology, Inc. Method and circuit for providing a memory device having hidden row access and row precharge times
JP3881477B2 (ja) 1999-09-06 2007-02-14 沖電気工業株式会社 シリアルアクセスメモリ
DE102004051158B4 (de) * 2003-10-30 2015-11-26 Polaris Innovations Ltd. Integrierter Halbleiterspeicher
US20060171234A1 (en) * 2005-01-18 2006-08-03 Liu Skip S DDR II DRAM data path
US20060161743A1 (en) * 2005-01-18 2006-07-20 Khaled Fekih-Romdhane Intelligent memory array switching logic
KR100631925B1 (ko) * 2005-01-28 2006-10-04 삼성전자주식회사 반도체 메모리 장치의 테스트 회로
US7817470B2 (en) * 2006-11-27 2010-10-19 Mosaid Technologies Incorporated Non-volatile memory serial core architecture
US7746710B2 (en) * 2008-01-10 2010-06-29 Micron Technology, Inc. Data bus power-reduced semiconductor storage apparatus
US8634268B2 (en) * 2010-10-27 2014-01-21 Taiwan Semiconductor Manufacturing Company, Ltd. Memory circuit having decoding circuits and method of operating the same
WO2015183834A1 (en) 2014-05-27 2015-12-03 Rambus Inc. Memory module with reduced read/write turnaround overhead
US10074413B2 (en) * 2016-03-17 2018-09-11 Toshiba Memory Corporation Semiconductor storage device

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52130536A (en) * 1976-04-26 1977-11-01 Toshiba Corp Semiconductor memory unit
US4290133A (en) * 1977-10-25 1981-09-15 Digital Equipment Corporation System timing means for data processing system
US4498155A (en) * 1979-11-23 1985-02-05 Texas Instruments Incorporated Semiconductor integrated circuit memory device with both serial and random access arrays
JPS56101687A (en) * 1979-12-27 1981-08-14 Fujitsu Ltd Semiconductor memory circuit
US4630230A (en) * 1983-04-25 1986-12-16 Cray Research, Inc. Solid state storage device
US4646270A (en) * 1983-09-15 1987-02-24 Motorola, Inc. Video graphic dynamic RAM
DD220394A1 (de) * 1983-10-03 1985-03-27 Zeiss Jena Veb Carl Auflichtlaengenmesssystem
JPS60157798A (ja) 1984-01-26 1985-08-19 Toshiba Corp 半導体メモリ
US4599709A (en) * 1984-02-17 1986-07-08 At&T Bell Laboratories Byte organized static memory
JPS618785A (ja) * 1984-06-21 1986-01-16 Fujitsu Ltd 記憶装置アクセス制御方式
US4725945A (en) * 1984-09-18 1988-02-16 International Business Machines Corp. Distributed cache in dynamic rams
US4663742A (en) * 1984-10-30 1987-05-05 International Business Machines Corporation Directory memory system having simultaneous write, compare and bypass capabilites
JPS61114351A (ja) 1984-11-08 1986-06-02 Hitachi Ltd メモリ制御装置
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
JPS6240693A (ja) * 1985-08-16 1987-02-21 Fujitsu Ltd ニブル・モ−ド機能を有する半導体記憶装置
JPH0821231B2 (ja) * 1986-08-13 1996-03-04 株式会社日立製作所 半導体メモリ
US4800530A (en) * 1986-08-19 1989-01-24 Kabushiki Kasiha Toshiba Semiconductor memory system with dynamic random access memory cells
JPS6350998A (ja) * 1986-08-19 1988-03-03 Toshiba Corp 半導体記憶装置
JPS6352397A (ja) * 1986-08-20 1988-03-05 Toshiba Corp 半導体記憶装置
JPS6363198A (ja) * 1986-09-03 1988-03-19 Toshiba Corp 半導体記憶装置
JP2509577B2 (ja) * 1986-09-03 1996-06-19 株式会社東芝 半導体記憶装置
US5018109A (en) * 1987-01-16 1991-05-21 Hitachi, Ltd. Memory including address registers for increasing access speed to the memory
IT1225476B (it) * 1987-10-14 1990-11-14 Point Universal Spa Struttura di riga ottica ad elementi modulari componibili
JP2895488B2 (ja) * 1988-04-18 1999-05-24 株式会社東芝 半導体記憶装置及び半導体記憶システム

Also Published As

Publication number Publication date
JPH01267893A (ja) 1989-10-25
DE3912695A1 (de) 1989-10-26
US20020089891A1 (en) 2002-07-11
US6301185B1 (en) 2001-10-09
US6538952B2 (en) 2003-03-25
KR950007834B1 (ko) 1995-07-20
DE3912695C2 (de) 1998-06-18
JP2895488B2 (ja) 1999-05-24
US6118721A (en) 2000-09-12
US20020031037A1 (en) 2002-03-14
US6404696B1 (en) 2002-06-11
US5497351A (en) 1996-03-05

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G160 Decision to publish patent application
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FPAY Annual fee payment

Payment date: 20090626

Year of fee payment: 15

EXPY Expiration of term