KR840005926A - 반도체 집적 회로 장치의 제조 방법 - Google Patents

반도체 집적 회로 장치의 제조 방법 Download PDF

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KR840005926A
KR840005926A KR1019830003011A KR830003011A KR840005926A KR 840005926 A KR840005926 A KR 840005926A KR 1019830003011 A KR1019830003011 A KR 1019830003011A KR 830003011 A KR830003011 A KR 830003011A KR 840005926 A KR840005926 A KR 840005926A
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forming
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semiconductor layer
epitaxial semiconductor
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노리오(외 1) 안자기
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미쓰다 가쓰시게
가부시기 가이샤 히다찌세이사꾸쇼
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Abstract

내용 없음

Description

반도체 집적 회로 장치의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도~제3도는 본 발명에 의한 Bi-CMOS IC 제조공정의 실시예를 도시한 공정 단면도.

Claims (5)

  1. 다음 사항을 포함한 반도체 집적 회로 장치의 제조방법.
    (1) 제1도전형 불순물을 함유한 기판 주면의 다수개소에 제1도전형 불순물을 부분적으로 도입하고, 기판보다도 그농도인 다수개의 불순물 도입영역을 하는 공정.
    (2) 상기 기판의 주면 위에 제2도전형 불순물을 함유한 에피택셜 반도체 층을 형성하는 공정.
    (3) 상기 다수개의 불순물 도입 영역 위에 위치하는 에피택셜 반도체 층 주면의 각각의 개소에 동시에 제1도전형 불순물을 도입하는 공정.
    (4) 상기 다수개의 불순물 도입 영역의 제1도전형 불순물을 에피택셜 반도체 층내로 확대 확산시키고, 동시에, 에피택셜 반도체 층내로 확대 확산시키고, 동시에, 에피택셜 반도체 층 주면에 도입된 제1도전형 불순물을 확대 확산하여 각각의 확산에 의해 형성되는 확산층을 연결해서 분리 영역과 MOSFET를 형성하기 위한 반도체 영역을 형성하는 공정.
    (5) 상기 분리 영역의 주표면에 두꺼운 산화막을 형성하는 공정.
    (6) 상기 반도체 영역에 절연 게이트 형 전계효과 트랜지스터를 형성하는 공정.
    (7) 상기 에피택셜 반도체 층의 일부에 바이 포올러 트랜지스터를 형성하는 공정.
  2. 분리 영역의 주표면에 두꺼운 산화막을 형성한 후, 그 두꺼운 산화막을 마스크로 해서, 에피택셜 반도체 주면의 일부에 선택적으로 제1도전형 불순물을 도입하여 바이포올러 트랜지스터의 베이스를 형성하는 공정을 함유하는 특허청구 범위 제1항의 반도체 집적회로 장치의 제조 방법.
  3. 바이포올러 트랜지스터의 베이스 내에 제2도전형 불순물을 도입하여, 에미터를 형성함과 동시에, 제1도전형 반도체 영역 내에로 제2도전형 불순물을 도입하여 MOSFET의 소오스 드레인을 형성하는 공정을 함유하는 특허청구 범위 제2항의 반도체 집적회로 장치의 제조 방법.
  4. 다음 사항을 포함한 반도체 집적회로 장치의 제조 방법.
    (1) 제1도전형 불순물을 함유한 기판 주면의 다수 개소에 제1도전형 불순물을 부분적으로 도입하여 기판보다도 고농도인 다수개의 불순물 도입 영역을 형성하는 공정.
    (2) 상기 기판의 주면 위에 제2도전형 불순물을 함유한 에피택셜 반도체 층을 형성하는 공정.
    (3) 상기 다수 개의 불순물 도입 영역 위에 위치하는 에피택셜 반도체 층 주면의 각각의 개소에 동시에, 제1도전형 불순물을 도입하는 공정.
    (4) 상기 다수개의 불순물 도입 영역의 제1돈전형 불순물을 에피택셜 반도체 층 안으로 확대 확선시킴과 동시에, 에피택셜 반도체 층 주면에 도입된 제1도전형 불순물을 확대 확산하여 각각의 확산에 의해서 형성되는 확산층을 연결하여 분리 영역과 MOSFET를 형성하기 위한 반도체 영역을 형성하는 공정.
    (5) 상기 에피택셜 반도체 층의 일부에 바이포올러 트랜지스터의 베이스를 형성하기 위하여, 제1도전형 불순물을 도입하여, 분리 영역의 주표면에 그 분리 영역보다도, 불순물 농도가 높은 고농도 영역을 형성하는 공정.
    (6) 상기 반도체 영역에 절연 게이트형 전계 효과 트랜지스터를 형성하는 공정.
    (7) 상기 에피택셜 반도체 층의 일부에 바이 포올러 트랜지스터를 형성하는 공정.
  5. 다음 사항을 포함한 반도체 집적회로 장치의 제조 방법.
    (1) 제1도전형 불순물을 함유한 기판 주면의 다수개소에 제1도전형 불순물을 부분적으로 도입하고, 기판보다도 고농도인 다수개의 불순물 도입 영역을 형성하는 공정.
    (2) 상기 기판의 주면위에 제2도전형 불순물을 함유한 에피택셜 반도체 층을 형성하는 공정.
    (3) 상기 다수개의 불순물 도입 영역 위에 위치하는 에피택셜 반도체 주면의 각각의 개소의 일부에 제1도전형 불순물을 도입하는 공정.
    (4) 상기 에피택셜 반도체 층 주면의 일부에 凹부를 형성하는 공정.
    (5) 열처리에 의해 상기 다수개의 불순물 도입 영역의 제1전형 불순물을 에피택셜 반도체 층 내에로 확대 확산하여 에피택셜 반도체 층 주면에 도입된 제1도전형 불순물을 확대 확산해서 형성되는 확산층과 연결하여, 에피택셜 반도체 층의 일부에 제1도전형의 반도체 영역을 형성함과 동시에 다른쪽에서는 상기 凹부하면에 달하는 분리 확산 영역을 형성하는 공정.
    (6) 상기 凹부의 주표면에 두꺼운 산화막을 형성하는 공정.
    (7) 상기 반도체 영역에 절연 게이트 형 전개 효과 트랜지스터를 형성하는 공정.
    (8) 상기 에피택셜 반도체 층의 일부에 바이포올러 트랜지스터를 형성하는 공정.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830003011A 1982-09-24 1983-07-01 반도체집적회로장치의 제조방법 KR920001403B1 (ko)

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JP164840 1982-09-24
JP57-164840 1982-09-24
JP57164840A JPS5955052A (ja) 1982-09-24 1982-09-24 半導体集積回路装置の製造方法

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KR840005926A true KR840005926A (ko) 1984-11-19
KR920001403B1 KR920001403B1 (ko) 1992-02-13

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US (1) US4529456A (ko)
JP (1) JPS5955052A (ko)
KR (1) KR920001403B1 (ko)
DE (1) DE3334337A1 (ko)
FR (1) FR2533751B1 (ko)
GB (1) GB2128024B (ko)
HK (1) HK71087A (ko)
IT (1) IT1168294B (ko)
MY (1) MY8700610A (ko)
SG (1) SG36887G (ko)

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JPS5955052A (ja) 1984-03-29
FR2533751A1 (fr) 1984-03-30
MY8700610A (en) 1987-12-31
FR2533751B1 (fr) 1988-11-10
SG36887G (en) 1987-09-18
GB8324163D0 (en) 1983-10-12
HK71087A (en) 1987-10-09
JPH0481337B2 (ko) 1992-12-22
KR920001403B1 (ko) 1992-02-13
GB2128024A (en) 1984-04-18
GB2128024B (en) 1986-01-02
IT8322983A0 (it) 1983-09-23
DE3334337A1 (de) 1984-03-29
IT1168294B (it) 1987-05-20
US4529456A (en) 1985-07-16

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