FR2358748A1 - Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede - Google Patents
Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procedeInfo
- Publication number
- FR2358748A1 FR2358748A1 FR7621646A FR7621646A FR2358748A1 FR 2358748 A1 FR2358748 A1 FR 2358748A1 FR 7621646 A FR7621646 A FR 7621646A FR 7621646 A FR7621646 A FR 7621646A FR 2358748 A1 FR2358748 A1 FR 2358748A1
- Authority
- FR
- France
- Prior art keywords
- aligning
- semi
- self
- elements
- embedded following
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000002955 isolation Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000010410 layer Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000011241 protective layer Substances 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
- H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
- Bipolar Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Procédé de réalisation de circuits intégrés à isolement latéral par cordons isolants. Un masque fondamental 5 est formé sur une première couche protectrice 3. Des fenêtres 13 sont obturées provisoirement pour réaliser des cordons isolants 17, puis un masque réplique est formé dans la couche 3 et définit les régions, de préférence implantées. Application aux circuits intégrés en silicium à isolement latéral par oxyde.
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7621646A FR2358748A1 (fr) | 1976-07-15 | 1976-07-15 | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
DE19772729973 DE2729973A1 (de) | 1976-07-15 | 1977-07-02 | Verfahren zur herstellung einer halbleiteranordnung |
CA282,208A CA1094429A (fr) | 1976-07-15 | 1977-07-07 | Methode de fabrication d'un dispositif a semiconducteurs |
GB29189/77A GB1580657A (en) | 1976-07-15 | 1977-07-12 | Semiconductor device manufacture |
NLAANVRAGE7707780,A NL188668C (nl) | 1976-07-15 | 1977-07-13 | Werkwijze voor de vervaardiging van een halfgeleiderinrichting. |
JP52084322A JPS6026301B2 (ja) | 1976-07-15 | 1977-07-15 | 半導体集積回路の製造方法 |
US06/367,506 US4443933A (en) | 1976-07-15 | 1982-04-12 | Utilizing multi-layer mask to define isolation and device zones in a semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR7621646A FR2358748A1 (fr) | 1976-07-15 | 1976-07-15 | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2358748A1 true FR2358748A1 (fr) | 1978-02-10 |
FR2358748B1 FR2358748B1 (fr) | 1978-12-15 |
Family
ID=9175756
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7621646A Granted FR2358748A1 (fr) | 1976-07-15 | 1976-07-15 | Procede d'autoalignement des elements d'un dispositif semi-conducteur et dispositif realise suivant ce procede |
Country Status (7)
Country | Link |
---|---|
US (1) | US4443933A (fr) |
JP (1) | JPS6026301B2 (fr) |
CA (1) | CA1094429A (fr) |
DE (1) | DE2729973A1 (fr) |
FR (1) | FR2358748A1 (fr) |
GB (1) | GB1580657A (fr) |
NL (1) | NL188668C (fr) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0000327A1 (fr) * | 1977-07-12 | 1979-01-24 | International Business Machines Corporation | Procédé de fabrication de dispositifs semiconducteurs intégrés auto-alignés |
EP0084399A2 (fr) * | 1982-01-18 | 1983-07-27 | Motorola, Inc. | Procédé d'isolation d'oxyde auto-alignée et dispositif |
EP0093786A1 (fr) * | 1982-05-06 | 1983-11-16 | Deutsche ITT Industries GmbH | Procédé de fabrication d'un circuit intégré monolithique comportant au moins un transistor à effet de champ à porte isolée et un transistor bipolair |
EP0122313A1 (fr) * | 1983-04-18 | 1984-10-24 | Deutsche ITT Industries GmbH | Procédé de fabrication d'un circuit intégré monolitique comportant au moins un transistor à effet de champ à grille isolée |
EP0295097A1 (fr) * | 1987-06-11 | 1988-12-14 | Fairchild Semiconductor Corporation | Fabrication d'une structure semi-conductrice |
US5055417A (en) * | 1987-06-11 | 1991-10-08 | National Semiconductor Corporation | Process for fabricating self-aligned high performance lateral action silicon-controlled rectifier and static random access memory cells |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55163400A (en) * | 1979-06-07 | 1980-12-19 | Tokyo Sogo Keibi Hoshiyou Kk | Liquid leak detection method in pipe line |
JPS58127374A (ja) * | 1982-01-25 | 1983-07-29 | Hitachi Ltd | 半導体装置の製造方法 |
JPS5955052A (ja) * | 1982-09-24 | 1984-03-29 | Hitachi Ltd | 半導体集積回路装置の製造方法 |
NL188923C (nl) * | 1983-07-05 | 1992-11-02 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4486266A (en) * | 1983-08-12 | 1984-12-04 | Tektronix, Inc. | Integrated circuit method |
US4569117A (en) * | 1984-05-09 | 1986-02-11 | Texas Instruments Incorporated | Method of making integrated circuit with reduced narrow-width effect |
US4663832A (en) * | 1984-06-29 | 1987-05-12 | International Business Machines Corporation | Method for improving the planarity and passivation in a semiconductor isolation trench arrangement |
US4797372A (en) * | 1985-11-01 | 1989-01-10 | Texas Instruments Incorporated | Method of making a merge bipolar and complementary metal oxide semiconductor transistor device |
US4669179A (en) * | 1985-11-01 | 1987-06-02 | Advanced Micro Devices, Inc. | Integrated circuit fabrication process for forming a bipolar transistor having extrinsic base regions |
US4692344A (en) * | 1986-02-28 | 1987-09-08 | Rca Corporation | Method of forming a dielectric film and semiconductor device including said film |
US5023690A (en) * | 1986-10-24 | 1991-06-11 | Texas Instruments Incorporated | Merged bipolar and complementary metal oxide semiconductor transistor device |
US6232232B1 (en) * | 1998-04-07 | 2001-05-15 | Micron Technology, Inc. | High selectivity BPSG to TEOS etchant |
US6660655B2 (en) * | 1999-10-12 | 2003-12-09 | Taiwan Semiconductor Manufacturing Company | Method and solution for preparing SEM samples for low-K materials |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3576630A (en) * | 1966-10-29 | 1971-04-27 | Nippon Electric Co | Photo-etching process |
US3488564A (en) * | 1968-04-01 | 1970-01-06 | Fairchild Camera Instr Co | Planar epitaxial resistors |
BE758009A (fr) * | 1969-10-27 | 1971-04-26 | Western Electric Co | Dispositif a impedance reglable pour circuit integre |
JPS5012995B1 (fr) * | 1970-02-09 | 1975-05-16 | ||
US3708360A (en) * | 1970-06-09 | 1973-01-02 | Texas Instruments Inc | Self-aligned gate field effect transistor with schottky barrier drain and source |
NL173110C (nl) * | 1971-03-17 | 1983-12-01 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting, waarbij op een oppervlak van een halfgeleiderlichaam een uit ten minste twee deellagen van verschillend materiaal samengestelde maskeringslaag wordt aangebracht. |
US3748187A (en) * | 1971-08-03 | 1973-07-24 | Hughes Aircraft Co | Self-registered doped layer for preventing field inversion in mis circuits |
US3860466A (en) * | 1971-10-22 | 1975-01-14 | Texas Instruments Inc | Nitride composed masking for integrated circuits |
US3899363A (en) * | 1974-06-28 | 1975-08-12 | Ibm | Method and device for reducing sidewall conduction in recessed oxide pet arrays |
US3948694A (en) * | 1975-04-30 | 1976-04-06 | Motorola, Inc. | Self-aligned method for integrated circuit manufacture |
US4135954A (en) * | 1977-07-12 | 1979-01-23 | International Business Machines Corporation | Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers |
-
1976
- 1976-07-15 FR FR7621646A patent/FR2358748A1/fr active Granted
-
1977
- 1977-07-02 DE DE19772729973 patent/DE2729973A1/de active Granted
- 1977-07-07 CA CA282,208A patent/CA1094429A/fr not_active Expired
- 1977-07-12 GB GB29189/77A patent/GB1580657A/en not_active Expired
- 1977-07-13 NL NLAANVRAGE7707780,A patent/NL188668C/xx not_active IP Right Cessation
- 1977-07-15 JP JP52084322A patent/JPS6026301B2/ja not_active Expired
-
1982
- 1982-04-12 US US06/367,506 patent/US4443933A/en not_active Expired - Fee Related
Non-Patent Citations (1)
Title |
---|
NEANT * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0000327A1 (fr) * | 1977-07-12 | 1979-01-24 | International Business Machines Corporation | Procédé de fabrication de dispositifs semiconducteurs intégrés auto-alignés |
EP0084399A2 (fr) * | 1982-01-18 | 1983-07-27 | Motorola, Inc. | Procédé d'isolation d'oxyde auto-alignée et dispositif |
EP0084399A3 (en) * | 1982-01-18 | 1986-04-09 | Motorola, Inc. | Self-aligned oxide isolated process and device |
EP0093786A1 (fr) * | 1982-05-06 | 1983-11-16 | Deutsche ITT Industries GmbH | Procédé de fabrication d'un circuit intégré monolithique comportant au moins un transistor à effet de champ à porte isolée et un transistor bipolair |
EP0122313A1 (fr) * | 1983-04-18 | 1984-10-24 | Deutsche ITT Industries GmbH | Procédé de fabrication d'un circuit intégré monolitique comportant au moins un transistor à effet de champ à grille isolée |
EP0295097A1 (fr) * | 1987-06-11 | 1988-12-14 | Fairchild Semiconductor Corporation | Fabrication d'une structure semi-conductrice |
US5055417A (en) * | 1987-06-11 | 1991-10-08 | National Semiconductor Corporation | Process for fabricating self-aligned high performance lateral action silicon-controlled rectifier and static random access memory cells |
Also Published As
Publication number | Publication date |
---|---|
NL188668C (nl) | 1992-08-17 |
US4443933A (en) | 1984-04-24 |
NL188668B (nl) | 1992-03-16 |
DE2729973A1 (de) | 1978-01-19 |
FR2358748B1 (fr) | 1978-12-15 |
JPS5310289A (en) | 1978-01-30 |
GB1580657A (en) | 1980-12-03 |
NL7707780A (nl) | 1978-01-17 |
JPS6026301B2 (ja) | 1985-06-22 |
CA1094429A (fr) | 1981-01-27 |
DE2729973C2 (fr) | 1987-03-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
CA | Change of address | ||
CD | Change of name or company name | ||
ST | Notification of lapse |