JP5684450B2 - 半導体装置及びその製造方法 - Google Patents
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Description
本発明の半導体装置は、MOS構造に代えてバイポーラトランジスタを有する半導体装置であっても良い。かかるバイポーラトランジスタを有する場合の半導体装置の構造を図14乃至図16を参照しつつ説明する。
11 P型半導体基板
12 N型エピタキシャル層
13 N型埋め込み層
14 層間絶縁層
15a LDMOSソース電極
15b HVMOSソース電極
16a LDMOSドレイン電極
16b HVMOSドレイン電極
17a〜17d 高濃度P型領域(P+領域)
18 第1のN型高濃度領域(N+領域)
19 P型ボディ層
20a〜20d フィールド酸化膜
21a 第2のN型高濃度領域(LDMOSチャネルストッパー)
21b 第3のN型高濃度領域(HVMOSチャネルストッパー)
22 P型ドリフト層
23 P型分離領域
24a LDMOSゲート酸化膜
24b HVMOSゲート酸化膜
25a LDMOSゲート電極
25b HVMOSゲート電極
26a〜26c コンタクト配線
Claims (9)
- 第1導電型半導体層と、
前記第1導電型半導体層上に形成され、少なくとも1つの半導体素子がその表面領域に形成された第2導電型素子形成領域を有する第2導電型半導体層と、
前記第2導電型半導体層に形成され当該第2導電型半導体層の前記第2導電型素子形成領域を互いに絶縁しつつ複数に分離する第1導電型素子分離領域と、
前記第1導電型素子分離領域上に形成され、前記第2導電型半導体層に延在するフィールド酸化膜と、
前記第1導電型半導体層上において前記第2導電型半導体層に接し且つ前記第1導電型素子分離領域から離間して形成された第2導電型埋め込み領域と、を有する半導体装置であって、
前記第2導電型半導体層の表面に形成され、前記半導体素子を囲み且つ前記第1導電型素子分離領域から離間して形成された第2導電型高濃度領域を更に有し、
前記第2導電型高濃度領域は、前記フィールド酸化膜の下面において、前記第2導電型埋め込み領域と前記第1導電型素子分離領域との離間距離よりも前記第2導電型高濃度領域と該第1導電型素子分離領域との離間距離のほうが短くなる位置に形成されていることを特徴とする半導体装置。 - 前記第1導電型素子分離領域から前記第2導電型高濃度領域までの離間距離は、前記第1導電型素子分離領域から前記第2導電型埋め込み領域までの離間距離の40%〜80%であることを特徴とする請求項1に記載の半導体装置。
- 前記第2導電型高濃度領域の少なくとも一部は、前記第2導電型埋め込み領域と対向していることを特徴とする請求項1又は2に記載の半導体装置。
- 前記第2導電型高濃度領域は、前記半導体素子を環状に取り囲んでいることを特徴とする請求項1乃至3のいずれか1に記載の半導体装置。
- 前記第2導電型高濃度領域は、前記半導体素子と接していないことを特徴とする請求項1乃至4のいずれかに1に記載の半導体装置。
- 第1導電型半導体基板を準備する準備工程と、
前記第1導電型半導体基板の表面に断続部を含む第2導電型埋め込み層を形成する埋め込み層形成工程と、
前記第1導電型半導体基板及び前記第2導電型埋め込み層上に第2導電型素子形成層を形成する素子層形成工程と、
前記第2導電型素子形成層の表面にフィールド酸化膜を形成する工程と、
前記第2導電型素子形成層の表面領域に前記第2導電型素子形成層よりも不純物濃度が高い第2導電型高濃度領域を形成する高濃度領域形成工程と、
前記第2導電型埋め込み層の断続部上であって前記第2導電型高濃度領域から離間して第1導電型素子分離領域を形成する素子分離領域形成工程と、
前記第2導電型素子形成層の表面領域であって前記第2導電型高濃度領域によって囲まれた領域に半導体素子を形成する素子形成工程と、を有し、
前記第2導電型高濃度領域は、前記フィールド酸化膜の下面において、前記第2導電型埋め込み層と前記第1導電型素子分離領域との離間距離よりも前記第2導電型高濃度領域と該第1導電型素子分離領域との離間距離のほうが短くなる位置に形成されていることを特徴とする半導体装置の製造方法。 - 前記素子分離領域形成工程は、前記第1導電型素子分離領域から前記第2導電型高濃度領域までの離間距離が、前記第1導電型素子分離領域から前記第2導電型埋め込み層までの離間距離の40%〜80%となるように前記第1導電型素子分離領域を形成することを特徴とする請求項6に記載の半導体装置の製造方法。
- 前記高濃度領域形成工程は、前記第2導電型埋め込み層と少なくも一部が対向するように前記第2導電型高濃度領域を形成することを特徴とする請求項6又は7に記載の半導体装置の製造方法。
- 前記高濃度領域形成工程は、熱処理によって前記第2導電型高濃度領域上に素子分離絶縁膜を形成する加熱工程を有することを特徴とする請求項6乃至8のいずれか1に記載の半導体装置の製造方法。
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