KR20060047800A - 반도체 장치 및 반도체 장치의 제조 방법 - Google Patents
반도체 장치 및 반도체 장치의 제조 방법 Download PDFInfo
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- KR20060047800A KR20060047800A KR1020050039639A KR20050039639A KR20060047800A KR 20060047800 A KR20060047800 A KR 20060047800A KR 1020050039639 A KR1020050039639 A KR 1020050039639A KR 20050039639 A KR20050039639 A KR 20050039639A KR 20060047800 A KR20060047800 A KR 20060047800A
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02071—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a delineation, e.g. RIE, of conductive layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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Abstract
Description
샘플 | 손상층의 제어 없음 | 종래 방법에 의한 손상층 제거 | 제1 실시예에 따른 손상층 제거 |
컨택트 저항 | 200Ω | 60Ω | 40Ω |
Claims (10)
- 반도체 기판상에, 절연막을 형성하는 공정과,상기 절연막을, 드라이 공정에 의해 에칭하는 공정과,상기 에칭에 의해 상기 반도체 기판상에 발생한 손상층을, 열분해한 원자 상태의 수소에 의해, 소정의 온도 하에서 제거하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 열분해한 원자 상태의 수소는, 가열한 촉매체에 수소를 포함하는 분자를 접촉시켜 생성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 손상층의 제거 공정에서, 상기 반도체 기판의 서셉터 온도를 170℃ 이상으로 유지하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제2항에 있어서,상기 가열한 촉매는, 실리사이드화의 활성화 에너지가 1.8eV 이하인 금속을 포함하고, 그 금속을 상기 반도체 기판에 도입하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제1항에 있어서,상기 반도체 기판상에 폴리실리콘 플러그를 형성하는 공정과,상기 폴리실리콘 플러그 상에 퇴적한 절연막을 드라이 에칭하여 상기 폴리실리콘 플러그에 도달하는 컨택트홀을 형성하는 공정과,상기 드라이 에칭에 의해 상기 폴리실리콘 플러그 상에 발생한 손상층을, 열분해한 원자 상태의 수소에 의해 제거하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 반도체 기판상에, 절연막을 형성하는 공정과,상기 절연막 상에 전극으로 되는 도전막을 형성하는 공정과,상기 도전막을, 드라이 공정에 의해 에칭하는 공정과,상기 에칭에 의해 상기 반도체 기판상에 발생한 손상층 중 적어도 일부를, 상기 절연막 중 적어도 일부를 제거한 후, 열분해한 원자 상태의 수소에 의해, 소정의 온도 하에서 제거하는 공정을 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 반도체 기판상에, 절연막을 개재하여 게이트 전극을 형성하는 공정과,상기 게이트 전극의 측벽에, 드라이 에칭에 의해 사이드 월을 형성하는 공정과,상기 사이드 월의 형성에 의해 상기 반도체 기판상에 발생한 손상층 중 적어도 일부를, 열분해한 원자 상태의 수소에 의해, 소정의 온도 하에서 제거하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제6항 또는 제7항에 있어서,상기 열분해한 원자 상태의 수소는, 가열한 촉매체에 수소를 포함하는 분자를 접촉시켜 생성하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 제8항에 있어서,상기 가열한 촉매체는, 티타늄(Ti), 니켈(Ni), 코발트(Co), 플래티넘(Pt) 중 적어도 1개를 포함하고, 상기 손상층의 제거와 동시에, 또는 제거후에, 상기 촉매체의 구성 원소의 일부를 상기 반도체 기판에 도입하는 공정을 더 포함하는 것을 특징으로 하는 반도체 장치의 제조 방법.
- 반도체 기판과,상기 반도체 기판상에 절연막을 개재하여 위치하는 게이트 전극과,상기 게이트 전극의 측벽에 위치하는 사이드 월과,상기 게이트 전극의 양측의 반도체 기판에 형성된 불순물 확산 영역을 구비하고,상기 사이드 월 바닥면의 단면 형상은, 역사다리꼴 형상이고,상기 사이드 월의 외측에 위치하는 불순물 확산 영역 표면의 단면 형상은, 역사다리꼴 형상인 것을 특징으로 하는 반도체 장치.
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