JPWO2007083366A1 - 半導体装置、半導体ウエハ構造、及び半導体ウエハ構造の製造方法 - Google Patents
半導体装置、半導体ウエハ構造、及び半導体ウエハ構造の製造方法 Download PDFInfo
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- JPWO2007083366A1 JPWO2007083366A1 JP2007554766A JP2007554766A JPWO2007083366A1 JP WO2007083366 A1 JPWO2007083366 A1 JP WO2007083366A1 JP 2007554766 A JP2007554766 A JP 2007554766A JP 2007554766 A JP2007554766 A JP 2007554766A JP WO2007083366 A1 JPWO2007083366 A1 JP WO2007083366A1
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- film
- insulating film
- block
- region
- interlayer insulating
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- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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Abstract
Description
図1〜図19は、本発明の第1実施形態に係る半導体ウエハ構造の製造途中の断面図である。
図28〜図38は、本発明の第2実施形態に係る半導体ウエハ構造の製造途中の断面図である。
図44は、比較例に係る半導体ウエハ構造の断面図である。なお、図44では、第1実施形態で説明した要素には第1実施形態と同じ符号を付してあり、その説明については省略する。
Claims (20)
- 回路形成領域と周辺領域とを有する半導体基板と、
前記半導体基板の上に形成された下地絶縁膜と、
前記回路形成領域における前記下地絶縁膜の上に、下部電極、強誘電体材料よりなるキャパシタ誘電体膜、及び上部電極をこの順に形成してなるキャパシタと、
前記キャパシタの上方に形成された最上層の層間絶縁膜と、
前記周辺領域における前記半導体基板上に形成され、少なくとも前記層間絶縁膜の上面に達する高さを有すると共に、前記回路形成領域を囲う耐湿リングと、
前記耐湿リング上とその周囲の前記層間絶縁膜上に形成されたブロック膜と、
前記周辺領域の前記層間絶縁膜の上に形成され、電極パッドを備えると共に、ダイシング面に断面が露出する電極用導体パターンと、
を有することを特徴とする半導体装置。 - 前記耐湿リングは、フェンス状導電性プラグとリング状導体パターンとを交互に積み重ねてなり、最上層に前記フェンス状導電性プラグを有することを特徴とする請求項1に記載の半導体装置。
- 前記フェンス状導電性プラグはタングステンを含み、前記リング状導体パターンはアルミニウムを含むことを特徴とする請求項2に記載の半導体装置。
- 前記ブロック膜は、前記チップ領域を囲うリング状であることを特徴とする請求項1に記載の半導体装置。
- 前記ブロック膜は単層の絶縁膜で構成されることを特徴とする請求項1に記載の半導体装置。
- 前記ブロック膜は、窒化シリコン膜、酸窒化シリコン膜、アルミナ膜、及び酸化チタン膜のいずれかであることを特徴とする請求項5に記載の半導体装置。
- 前記電極用導体パターンは、前記ブロック膜の上にも形成されることを特徴とする請求項5に記載の半導体装置。
- 前記電極用導体パターンは、アルミニウム膜を含む金属積層膜よりなることを特徴とする請求項5に記載の半導体装置。
- 前記ブロック膜は、ブロック導電膜とブロック絶縁膜とをこの順に形成してなることを特徴とする請求項1に記載の半導体装置。
- 前記ブロック絶縁膜は、前記ブロック導電膜の前記ダイシング面寄りの側面上と、該側面の横の前記層間絶縁膜上にも形成され、前記ブロック絶縁膜の断面が前記ダイシング面に露出することを特徴とする請求項9に記載の半導体装置。
- 前記ブロック導電膜は、アルミニウム膜を含む金属積層膜よりなり、
前記ブロック絶縁膜は、窒化シリコン膜、酸窒化シリコン膜、アルミナ膜、及び酸化チタン膜のいずれかであることを特徴とする請求項9に記載の半導体装置。 - 前記層間絶縁膜の上に形成された下部導体パターンと、
前記層間絶縁膜上と前記ブロック膜上とに形成され、前記下部導体パターンの上に開口を備えたパッシベーション膜と、
前記パッシベーション膜上と、前記開口内の前記下部導体パターン上とに形成された上部導体パターンとを有し、
前記電極用導体パターンが前記下部導体パターンと前記上部導体パターンとにより構成されることを特徴とする請求項9に記載の半導体装置。 - 前記下部導体パターンと前記上部導体パターンは、それぞれアルミニウム膜を含む金属積層膜よりなることをと特徴とする請求項12に記載の半導体装置。
- 前記層間絶縁膜は、キャパシタ保護絶縁膜を含む積層膜で構成されることを特徴とする請求項1に記載の半導体装置。
- 前記キャパシタ保護絶縁膜は、アルミナ膜又は酸化チタン膜であることを特徴とする請求項14に記載の半導体装置。
- チップ領域とスクライブ領域とを有する半導体基板と、
前記半導体基板の上に形成された下地絶縁膜と、
前記チップ領域の回路形成領域における前記下地絶縁膜の上に、下部電極、強誘電体材料よりなるキャパシタ誘電体膜、及び上部電極をこの順に形成してなるキャパシタと、
前記キャパシタの上方に形成された最上層の層間絶縁膜と、
前記チップ領域の周辺領域における前記半導体基板上に形成され、少なくとも前記層間絶縁膜の上面に達する高さを有すると共に、前記回路形成領域を囲う耐湿リングと、
前記耐湿リング上とその周囲の前記層間絶縁膜上に形成されたブロック膜と、
前記層間絶縁膜上と前記ブロック膜上とに形成され、前記周辺領域から前記スクライブ領域に延在し、該周辺領域に電極パッドを備えると共に、前記スクライブ領域に試験用パッドを備えた電極用導体パターンと、
を有することを特徴とする半導体ウエハ構造。 - 前記耐湿リングは、フェンス状導電性プラグとリング状導体パターンとを交互に積み重ねてなり、最上層に前記フェンス状導電性プラグを有することを特徴とする請求項16に記載の半導体ウエハ構造。
- 前記ブロック膜は、窒化シリコン膜、酸窒化シリコン膜、アルミナ膜、及び酸化チタン膜のいずれかよりなる単層の絶縁膜であることを特徴とする請求項16に記載の半導体ウエハ構造。
- 前記ブロック膜は、ブロック導電膜とブロック絶縁膜とをこの順に形成してなることを特徴とする請求項16に記載の半導体ウエハ構造。
- チップ領域とスクライブ領域とを有する半導体基板の上に下地絶縁膜を形成する工程と、
前記チップ領域の回路形成領域における前記下地絶縁膜の上に、下部電極、強誘電体材料よりなるキャパシタ誘電体膜、及び上部電極をこの順に積層してキャパシタを形成する工程と、
前記キャパシタの上方に最上層の層間絶縁膜を形成する工程と、
前記チップ領域の周辺領域における前記半導体基板上に、少なくとも前記層間絶縁膜の上面に達する高さを有すると共に、前記回路形成領域を囲う耐湿リングを形成する工程と、
前記耐湿リング上とその周囲の前記層間絶縁膜上にブロック膜を形成する工程と、
前記層間絶縁膜上と前記ブロック膜上とに、前記周辺領域から前記スクライブ領域に延在し、該周辺領域に電極パッドを備えると共に、前記スクライブ領域に試験用パッドを備えた電極用導体パターンを形成する工程と、
を有することを特徴とする半導体ウエハ構造の製造方法。
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JP5862290B2 (ja) * | 2011-12-28 | 2016-02-16 | 富士通セミコンダクター株式会社 | 半導体装置とその製造方法 |
TWI440412B (zh) * | 2011-12-28 | 2014-06-01 | Princo Corp | 超薄多層基板之封裝方法 |
JP6132525B2 (ja) | 2012-11-30 | 2017-05-24 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
KR102152256B1 (ko) | 2014-02-11 | 2020-09-04 | 에스케이하이닉스 주식회사 | 직류-직류 변환기 및 그 형성 방법 |
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JP6577899B2 (ja) * | 2016-03-31 | 2019-09-18 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR102546684B1 (ko) * | 2017-11-29 | 2023-06-23 | 삼성전자주식회사 | 반도체 소자 및 이를 포함하는 반도체 웨이퍼, 그리고 반도체 패키지 |
US11158555B2 (en) * | 2018-03-29 | 2021-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having sensor die with touch sensing electrode, and method of fabricating the same |
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