JPS647637A - Multilayer interconnection for integrated circuit - Google Patents

Abstract

PURPOSE:To shorten the forming time of through-holes and wirings, to form fine through-hole patterns and to shape a multilayer interconnection having excellent accuracy with superior productivity by forming the through-holes at every inter-layer film and shaping relay wirings connecting wiring layers at every wiring layer through the through-holes. CONSTITUTION:In a multilayer interconnection in which wiring layers 2 and inter-layer films 3 are laminated alternately onto a substrate 1, through-holes 5 are shaped at every inter-layer film 3, and relay wirings 4 connecting the wiring layers 2 through the through-holes 5 are formed at every wiring layer 2. A first layer wiring 2a is shaped onto the insulated substrate 1, and coated with a first inter-layer film 3a, a second layer wiring 2b is formed onto the first inter-layer film 3a, and the relay wiring 4 is connected to the first layer wiring 2a by a through-hole 5a shaped to the first inter-layer film 3a. The second layer wiring 2b is coated with a second inter-layer film 3b, and a third layer wiring 2c is formed onto the film 3b. The third layer wiring 2c is connected to the relay wiring 4 by a through-hole 5b shaped to the second inter- layer film 3b, and the third layer wiring 2c is connected to the first layer wiring 2a through the relay wiring 4.