JPS6457736A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS6457736A JPS6457736A JP21431187A JP21431187A JPS6457736A JP S6457736 A JPS6457736 A JP S6457736A JP 21431187 A JP21431187 A JP 21431187A JP 21431187 A JP21431187 A JP 21431187A JP S6457736 A JPS6457736 A JP S6457736A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- integrated circuit
- system clock
- chip
- whole surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To lay out wirings for other signals easily by assigning a wiring as an uppermost layer formed onto approximately the whole surface of a chip as a wiring for an arbitrary signal such as a system clock in a semiconductor integrated circuit with multilayer metallic interconnections. CONSTITUTION:In a CMOS integrated circuit having three-layer aluminum wiring structure, an aluminum wiring 21 as an uppermost layer is evaporated and formed onto approximately the whole surface on a chip, assigned as a wiring such as a system clock wiring, and brought into contact with a signal wiring 19 requiring clock supply in second layer wirings. Since the wiring resistance of the metallic wiring 21 shaped onto approximately the whole surface on the chip is reduced extremely, the metallic wiring 21 is particularly proper when it is used as the system clock wiring, etc., supplying a system clock for synchronously operating the whole integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21431187A JPS6457736A (en) | 1987-08-28 | 1987-08-28 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21431187A JPS6457736A (en) | 1987-08-28 | 1987-08-28 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6457736A true JPS6457736A (en) | 1989-03-06 |
Family
ID=16653642
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21431187A Pending JPS6457736A (en) | 1987-08-28 | 1987-08-28 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6457736A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206273A (en) * | 1991-11-14 | 1993-08-13 | Nec Corp | Semiconductor integrated circuit |
| US5446410A (en) * | 1992-04-20 | 1995-08-29 | Matsushita Electric Industrial Co.,Ltd. | Semiconductor integrated circuit |
| JPH11175184A (en) * | 1997-12-12 | 1999-07-02 | Fujitsu Ltd | Clock distributing circuit for semiconductor integrated circuit |
| DE10104233A1 (en) * | 2001-01-31 | 2002-08-22 | Tech Uni Muenchen Lehrstuhl Fu | Line layout method for wiring plane for integrated semiconductor device positions lines in wiring plane in order of their circuit activity |
-
1987
- 1987-08-28 JP JP21431187A patent/JPS6457736A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206273A (en) * | 1991-11-14 | 1993-08-13 | Nec Corp | Semiconductor integrated circuit |
| US5446410A (en) * | 1992-04-20 | 1995-08-29 | Matsushita Electric Industrial Co.,Ltd. | Semiconductor integrated circuit |
| USRE36278E (en) * | 1992-04-20 | 1999-08-24 | Matsushita Electric Industrial Co.,Ltd. | Semiconductor integrated circuit |
| JPH11175184A (en) * | 1997-12-12 | 1999-07-02 | Fujitsu Ltd | Clock distributing circuit for semiconductor integrated circuit |
| DE10104233A1 (en) * | 2001-01-31 | 2002-08-22 | Tech Uni Muenchen Lehrstuhl Fu | Line layout method for wiring plane for integrated semiconductor device positions lines in wiring plane in order of their circuit activity |
| DE10104233B4 (en) * | 2001-01-31 | 2006-08-03 | Technische Universität München Lehrstuhl für integrierte Schaltungen | Method for assigning lines to wiring levels for semiconductor integrated circuit devices |
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