JPS6218069A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid layer short-circuit defects between wirings, stabilize current amplification and improve reliability by a method wherein wirings are composed of high melting point metal or its alloy and a layer insulation film is composed of oxide of polycrystalline silicon. CONSTITUTION:The first wirings 8a and 8b, which is connected to a P-type base 3 and an N-type emitter 4 through contact holes 6 and 7, and the first wiring 8c which is connected to a semiconductor substrate 1 through a contact hole 9 are formed on an insulation film 5. Those first wirings 8a-8c are composed of high melting point metal such as W or Mo or alloy of them and a layer insulation film 10 is formed on the insulation film 5 so as to cover the first wirings 8a-8c. The layer insulation film 10 is composed of oxide of polycrystalline silicon and the second wiring 12, which is connected to the first wiring 8c through a contact hole 11, and a passivation film 13, which covers the second wiring 12, are formed on the layer insulation film 10. With this constitution, layer short-circuit defects between wirings can be avoided and current amplification can be stabilized.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

伜→　　　Ｊ７　」　−二　【　二　１ノ　、ラ　フ　
カ竺話、ｒ　也　７　半導体装置は、所定の能動領域を
設けた半導体基板上に能動領域の所定部分に接続する第
１層配線を形成し、第１層配線の相互を絶縁膜で分離す
ると共に、第１層配線を覆う層間絶縁膜を前記絶縁膜上
に形成し、更に眉間絶縁膜上にコンタクトホールを介し
て第１層配線に接続する第２層配線を設けた構造を有し
ている。伜→J7” -2 [2 1ノ, rough
In a semiconductor device, a first layer wiring is formed on a semiconductor substrate having a predetermined active area, and is connected to a predetermined part of the active area, and the first layer wiring is separated from each other by an insulating film. In addition, an interlayer insulating film covering the first layer wiring is formed on the insulating film, and a second layer wiring is further provided on the glabella insulating film to connect to the first layer wiring via a contact hole. There is.

然るに１第１、第２配線はアルミニウムで形成されてお
シ、層間絶縁膜はプラズマＣＶＤ膜、常圧ＣＶＤ膜等で
形成されていた。このため、配線がアルミニウムで形成
されていることから、層間絶縁膜中に発生するヒロック
欠陥を除去するための熱処理を施すことができず、層間
ショート不良率が高くなる問題があった。また、層間絶
縁膜中にヒロック等の欠陥が発生し易すいことから、ト
ランジスタの電流増幅率が不安定になυ、素子の信頼性
を低下する問題があった。However, the first and second wirings are made of aluminum, and the interlayer insulating film is made of a plasma CVD film, an atmospheric pressure CVD film, or the like. Therefore, since the wiring is made of aluminum, it is not possible to perform heat treatment to remove hillock defects occurring in the interlayer insulating film, resulting in a problem of high interlayer short failure rate. Furthermore, since defects such as hillocks are likely to occur in the interlayer insulating film, there is a problem that the current amplification factor of the transistor becomes unstable υ and the reliability of the device is reduced.

〔発明の目的〕[Purpose of the invention]

本発明は、配線相互間の眉間ショート不良の発生を防＋
）−すると共に、電流増幅率の安定を図って素子の信頼
性の向上を達成した半導体装置を提供することをその目
的とするものである。The present invention prevents the occurrence of short-circuit defects between wiring lines.
)-- and at the same time, it is an object of the present invention to provide a semiconductor device in which the reliability of the element is improved by stabilizing the current amplification factor.

〔発明の概要〕[Summary of the invention]

本発明は、配線を高融点金属またはその合金で形成し、
眉間絶縁膜を多結晶シリコンの酸化物で形成したことに
より、”配線相互間の眉間ショート不良の発生を防止す
ると共に、電流増幅率の安定によシ信頼性の向上を達成
した半導体装置である。In the present invention, the wiring is formed of a high melting point metal or an alloy thereof,
By forming the glabellar insulating film with polycrystalline silicon oxide, this semiconductor device prevents the occurrence of glabellar short-circuit defects between wiring lines and improves reliability by stabilizing the current amplification factor. .

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例について図面を参照して説明する
。第１図は、本発明の一実施例の概略構成を示す説明図
である。図中１は、高濃度の埋込領域２を有する半導体
基板である。半導体基板１の主面側には、所定の拡散深
さのＰペース３が形成されている。Ｐペース３内には、
所定の拡散深さのＮエミッタ４が形成されている。半導
体基板１の主面は、絶縁膜５が形成されている。絶縁膜
５には、Ｐペース３、Ｎエミッタ４の夫々に通じるコン
タクトホール６．７が開口されている。絶縁膜５上には
、フンタクトホールｅ　、　ｙ　ヲ介シーｃｐ　ヘース
３、Ｎエミッタ４に接続する第１配線８ｍ、８ｂが形成
されている。また、絶縁膜５上には、コンタクトホール
９を介して半導体基板１に接続する第１配線８ｃが形成
されている。これらの第１配線８ｇ、８ｂ、８ｃは、Ｗ
　、Ｍｏ等の高融点金属或はこれらの合金で形成されて
いる。絶縁膜５上には、第１配線８ｍ、８ｂ、Ｂｅを覆
うように層間絶縁膜１０が形成されている。眉間絶縁膜
１０は、多結晶シリコンの酸化物で形成されている。層
間絶縁膜１０上には、コンタクトホール１１を介して第
１配線８ｃに接続する第２配線１２が形成されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. In the figure, reference numeral 1 denotes a semiconductor substrate having a high concentration buried region 2. As shown in FIG. A P paste 3 having a predetermined diffusion depth is formed on the main surface side of the semiconductor substrate 1. Inside P Pace 3,
An N emitter 4 with a predetermined diffusion depth is formed. An insulating film 5 is formed on the main surface of the semiconductor substrate 1 . Contact holes 6.7 are opened in the insulating film 5, communicating with the P space 3 and the N emitter 4, respectively. On the insulating film 5, first wirings 8m and 8b are formed which are connected to the conductive holes e, y, the capacitor 3, and the N emitter 4. Further, on the insulating film 5, a first wiring 8c is formed which is connected to the semiconductor substrate 1 via the contact hole 9. These first wirings 8g, 8b, 8c are W
, Mo, etc., or an alloy thereof. An interlayer insulating film 10 is formed on the insulating film 5 so as to cover the first wirings 8m, 8b, and Be. The glabellar insulating film 10 is made of polycrystalline silicon oxide. A second wiring 12 is formed on the interlayer insulating film 10 to connect to the first wiring 8c via a contact hole 11.

層間絶縁膜１０上には、第２配線１２を覆うパッジペー
ジｌン膜１３が形成されている。A padding film 13 covering the second interconnect 12 is formed on the interlayer insulating film 10 .

ここで、第１配線ＩＪ＊、８ｂ、Ｂｅの形成は、高融点
金属或はその合金をス・臂ツタ法や化学気相反応で堆積
した後、周知の写真蝕刻法によってパターニングするこ
とにより容易に行われる。Here, the first wirings IJ*, 8b, and Be can be easily formed by depositing a high-melting point metal or its alloy by a starburst method or chemical vapor phase reaction, and then patterning it by a well-known photolithography method. It will be held on.

眉間絶縁膜１０の形成は、例えば減圧化学気相反応によ
って８１Ｈ４ガスを熱分解して多結晶シリコンを所定量
だけ堆積し、これにＨ２Ｏ＋　Ｈ２の雰囲気下で５００
℃以上の熱処理を施すことによシ、容易に行われる。層
間絶縁膜１０の形成に際しては、その内部にリン、？ロ
ン、ヒ素等の不純物元素を含有させるようにしても良い
。The glabella insulating film 10 is formed by depositing a predetermined amount of polycrystalline silicon by thermally decomposing 81H4 gas by, for example, a low-pressure chemical vapor phase reaction, and then depositing polycrystalline silicon in a predetermined amount in an atmosphere of H2O+H2.
This can be easily achieved by heat treatment at temperatures above ℃. When forming the interlayer insulating film 10, phosphorus, ? Impurity elements such as iron and arsenic may also be contained.

このように構成された半導体装置２０によれば、第１配
９８　ｍ　、　８　ｂ　、　８　ｃが高融点金属或はそ
の合金で形成されているので、例えば５００℃以上の高
温熱処理によりて、層間絶縁膜１０中のヒロック等の欠
陥を除去するための処理を施すことができる。このため
所謂配線相互間での層間シ１−ト不良の発生を防止する
ことができる。因みに実施例の半導体装置２０では、イ
ニシャル不良率及び熱シ嘗ツクテスト（ＴＣＴ。According to the semiconductor device 20 configured in this manner, since the first layers 98m, 8b, and 8c are made of a high-melting point metal or an alloy thereof, the interlayers can be bonded by heat treatment at a high temperature of 500°C or higher, for example. A process for removing defects such as hillocks in the insulating film 10 can be performed. Therefore, it is possible to prevent the occurrence of so-called interlayer sheet defects between wirings. Incidentally, in the semiconductor device 20 of the embodiment, the initial failure rate and the thermal shock test (TCT) were evaluated.

ａｔ−６０〜１７５℃）不良率ともに約０％であったが
、従来の半導体装置では前者が３〜５％、後者が１〜２
％であった。(at -60~175℃) Both defective rates were approximately 0%, but in conventional semiconductor devices, the former was 3~5% and the latter was 1~2%.
%Met.

＊＋ｒａＭ錦套あ胛１１ｎ売ｌｒゐλｎ）体Ｌノ１！−
−督＾多結晶シリコンの酸化物の状態で形成されている
ので、そのノ等ツシペーシ四ノ効果によって電流増幅率
を安定にして素子の信頼性及び歩留シを著しく向上させ
ることができる。因みに、実施例の半導体装置２０では
、１６８時間の通電−の前後での電流増幅率の変動は、
第２図に示す如く極めて少ないが、従来の半導体装置で
は同図に併記する通電、通電の前後で電流増幅率が大き
く変化し、不安定であることが確認された。*+raM Nishikimanto 11n sale lrゐλn) body L no 1! −
Since it is formed in the state of polycrystalline silicon oxide, the current amplification factor can be stabilized due to its uniformity effect, and the reliability and yield of the device can be significantly improved. Incidentally, in the semiconductor device 20 of the example, the variation in the current amplification factor before and after 168 hours of energization is as follows.
As shown in FIG. 2, although it is extremely rare, in the conventional semiconductor device, the current amplification factor changes greatly between energization and before and after energization, which is also shown in the same figure, and it has been confirmed that the current amplification factor is unstable.

また、実施例の学導体装置では、歩留シを従来のものに
比べて約１．２倍向上できることが実験的に確認された
。Furthermore, it has been experimentally confirmed that the yield of the conductor device of the example can be improved by about 1.2 times compared to the conventional device.

〔発明の効果〕 以上説明した如く、本発明に係る半導体装置によれば、
配線相互間の層間シ日−ト不良の発生を防止すると共に
、電流増幅率の安定を図って素子の信頼性を向上できる
ものである。[Effects of the Invention] As explained above, according to the semiconductor device according to the present invention,
This prevents the occurrence of interlayer sheet defects between wirings, stabilizes the current amplification factor, and improves the reliability of the device.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の一実施例の概略構成を示す説明図、
第２図は、通電後の電流増幅率と通電前の電流増幅率と
の関係を示す特性図である。 １・・・半導体基板、２・・・埋込領域、３・・・Ｐベ
ース、４・・・Ｎエミッタ、５・・・絶縁膜、６，７，
９゜１１・・・コンタクトホール、８ｇ、８ｂ、８ｃ・
・・第１配線、１０・・・層間絶縁膜、１２・・・第２
配線、１３・・・ノ４ツシペーション膜、２０・・・半
導体装置。 出願人代理人　　弁理士　鈴　江　武　彦第１図 第２図FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention,
FIG. 2 is a characteristic diagram showing the relationship between the current amplification factor after energization and the current amplification factor before energization. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buried region, 3... P base, 4... N emitter, 5... Insulating film, 6, 7,
9゜11...Contact hole, 8g, 8b, 8c.
...first wiring, 10...interlayer insulating film, 12...second
Wiring, 13... No. 4 sipation film, 20... Semiconductor device. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 　所定の素子を構成する能動領域を有する半導体基板と
、前記能動領域に接続して該半導体基板上に設けられ、
高融点金属またはその合金からなる第１配線と、該第１
配線の周囲を囲むようにして前記半導体基板上に設けら
れた絶縁膜と、前記第１配線を覆うように該絶縁膜上に
設けられ、多結晶シリコンの酸化物からなる層間絶縁膜
と、該層間絶縁膜のコンタクトホールを介して前記第１
配線に接続し、該層間絶縁膜上に設けられた第２配線と
を具備することを特徴とする半導体装置。a semiconductor substrate having an active region constituting a predetermined element; and a semiconductor substrate connected to the active region and provided on the semiconductor substrate,
a first wiring made of a high melting point metal or an alloy thereof;
an insulating film provided on the semiconductor substrate so as to surround the wiring; an interlayer insulating film made of polycrystalline silicon oxide and provided on the insulating film so as to cover the first wiring; and the interlayer insulating film. the first through the contact hole in the film.
A semiconductor device comprising: a second wiring connected to a wiring and provided on the interlayer insulating film.