JPS6218069A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6218069A JPS6218069A JP15651185A JP15651185A JPS6218069A JP S6218069 A JPS6218069 A JP S6218069A JP 15651185 A JP15651185 A JP 15651185A JP 15651185 A JP15651185 A JP 15651185A JP S6218069 A JPS6218069 A JP S6218069A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wirings
- insulating film
- insulation film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体装置に関する。[Detailed description of the invention] [Technical field of invention] The present invention relates to a semiconductor device.
伜→ J7 」 −二 【 二 1ノ 、ラ フ
カ竺話、r 也 7 半導体装置は、所定の能動領域を
設けた半導体基板上に能動領域の所定部分に接続する第
1層配線を形成し、第1層配線の相互を絶縁膜で分離す
ると共に、第1層配線を覆う層間絶縁膜を前記絶縁膜上
に形成し、更に眉間絶縁膜上にコンタクトホールを介し
て第1層配線に接続する第2層配線を設けた構造を有し
ている。伜→J7” -2 [2 1ノ, rough
In a semiconductor device, a first layer wiring is formed on a semiconductor substrate having a predetermined active area, and is connected to a predetermined part of the active area, and the first layer wiring is separated from each other by an insulating film. In addition, an interlayer insulating film covering the first layer wiring is formed on the insulating film, and a second layer wiring is further provided on the glabella insulating film to connect to the first layer wiring via a contact hole. There is.
然るに1第1、第2配線はアルミニウムで形成されてお
シ、層間絶縁膜はプラズマCVD膜、常圧CVD膜等で
形成されていた。このため、配線がアルミニウムで形成
されていることから、層間絶縁膜中に発生するヒロック
欠陥を除去するための熱処理を施すことができず、層間
ショート不良率が高くなる問題があった。また、層間絶
縁膜中にヒロック等の欠陥が発生し易すいことから、ト
ランジスタの電流増幅率が不安定になυ、素子の信頼性
を低下する問題があった。However, the first and second wirings are made of aluminum, and the interlayer insulating film is made of a plasma CVD film, an atmospheric pressure CVD film, or the like. Therefore, since the wiring is made of aluminum, it is not possible to perform heat treatment to remove hillock defects occurring in the interlayer insulating film, resulting in a problem of high interlayer short failure rate. Furthermore, since defects such as hillocks are likely to occur in the interlayer insulating film, there is a problem that the current amplification factor of the transistor becomes unstable υ and the reliability of the device is reduced.
本発明は、配線相互間の眉間ショート不良の発生を防+
)−すると共に、電流増幅率の安定を図って素子の信頼
性の向上を達成した半導体装置を提供することをその目
的とするものである。The present invention prevents the occurrence of short-circuit defects between wiring lines.
)-- and at the same time, it is an object of the present invention to provide a semiconductor device in which the reliability of the element is improved by stabilizing the current amplification factor.
本発明は、配線を高融点金属またはその合金で形成し、
眉間絶縁膜を多結晶シリコンの酸化物で形成したことに
より、”配線相互間の眉間ショート不良の発生を防止す
ると共に、電流増幅率の安定によシ信頼性の向上を達成
した半導体装置である。In the present invention, the wiring is formed of a high melting point metal or an alloy thereof,
By forming the glabellar insulating film with polycrystalline silicon oxide, this semiconductor device prevents the occurrence of glabellar short-circuit defects between wiring lines and improves reliability by stabilizing the current amplification factor. .
以下、本発明の実施例について図面を参照して説明する
。第1図は、本発明の一実施例の概略構成を示す説明図
である。図中1は、高濃度の埋込領域2を有する半導体
基板である。半導体基板1の主面側には、所定の拡散深
さのPペース3が形成されている。Pペース3内には、
所定の拡散深さのNエミッタ4が形成されている。半導
体基板1の主面は、絶縁膜5が形成されている。絶縁膜
5には、Pペース3、Nエミッタ4の夫々に通じるコン
タクトホール6.7が開口されている。絶縁膜5上には
、フンタクトホールe 、 y ヲ介シーcp ヘース
3、Nエミッタ4に接続する第1配線8m、8bが形成
されている。また、絶縁膜5上には、コンタクトホール
9を介して半導体基板1に接続する第1配線8cが形成
されている。これらの第1配線8g、8b、8cは、W
、Mo等の高融点金属或はこれらの合金で形成されて
いる。絶縁膜5上には、第1配線8m、8b、Beを覆
うように層間絶縁膜10が形成されている。眉間絶縁膜
10は、多結晶シリコンの酸化物で形成されている。層
間絶縁膜10上には、コンタクトホール11を介して第
1配線8cに接続する第2配線12が形成されている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention. In the figure, reference numeral 1 denotes a semiconductor substrate having a high concentration buried region 2. As shown in FIG. A P paste 3 having a predetermined diffusion depth is formed on the main surface side of the semiconductor substrate 1. Inside P Pace 3,
An N emitter 4 with a predetermined diffusion depth is formed. An insulating film 5 is formed on the main surface of the semiconductor substrate 1 . Contact holes 6.7 are opened in the insulating film 5, communicating with the P space 3 and the N emitter 4, respectively. On the insulating film 5, first wirings 8m and 8b are formed which are connected to the conductive holes e, y, the capacitor 3, and the N emitter 4. Further, on the insulating film 5, a first wiring 8c is formed which is connected to the semiconductor substrate 1 via the contact hole 9. These first wirings 8g, 8b, 8c are W
, Mo, etc., or an alloy thereof. An interlayer insulating film 10 is formed on the insulating film 5 so as to cover the first wirings 8m, 8b, and Be. The glabellar insulating film 10 is made of polycrystalline silicon oxide. A second wiring 12 is formed on the interlayer insulating film 10 to connect to the first wiring 8c via a contact hole 11.
層間絶縁膜10上には、第2配線12を覆うパッジペー
ジlン膜13が形成されている。A padding film 13 covering the second interconnect 12 is formed on the interlayer insulating film 10 .
ここで、第1配線IJ*、8b、Beの形成は、高融点
金属或はその合金をス・臂ツタ法や化学気相反応で堆積
した後、周知の写真蝕刻法によってパターニングするこ
とにより容易に行われる。Here, the first wirings IJ*, 8b, and Be can be easily formed by depositing a high-melting point metal or its alloy by a starburst method or chemical vapor phase reaction, and then patterning it by a well-known photolithography method. It will be held on.
眉間絶縁膜10の形成は、例えば減圧化学気相反応によ
って81H4ガスを熱分解して多結晶シリコンを所定量
だけ堆積し、これにH2O+ H2の雰囲気下で500
℃以上の熱処理を施すことによシ、容易に行われる。層
間絶縁膜10の形成に際しては、その内部にリン、?ロ
ン、ヒ素等の不純物元素を含有させるようにしても良い
。The glabella insulating film 10 is formed by depositing a predetermined amount of polycrystalline silicon by thermally decomposing 81H4 gas by, for example, a low-pressure chemical vapor phase reaction, and then depositing polycrystalline silicon in a predetermined amount in an atmosphere of H2O+H2.
This can be easily achieved by heat treatment at temperatures above ℃. When forming the interlayer insulating film 10, phosphorus, ? Impurity elements such as iron and arsenic may also be contained.
このように構成された半導体装置20によれば、第1配
98 m 、 8 b 、 8 cが高融点金属或はそ
の合金で形成されているので、例えば500℃以上の高
温熱処理によりて、層間絶縁膜10中のヒロック等の欠
陥を除去するための処理を施すことができる。このため
所謂配線相互間での層間シ1−ト不良の発生を防止する
ことができる。因みに実施例の半導体装置20では、イ
ニシャル不良率及び熱シ嘗ツクテスト(TCT。According to the semiconductor device 20 configured in this manner, since the first layers 98m, 8b, and 8c are made of a high-melting point metal or an alloy thereof, the interlayers can be bonded by heat treatment at a high temperature of 500°C or higher, for example. A process for removing defects such as hillocks in the insulating film 10 can be performed. Therefore, it is possible to prevent the occurrence of so-called interlayer sheet defects between wirings. Incidentally, in the semiconductor device 20 of the embodiment, the initial failure rate and the thermal shock test (TCT) were evaluated.
at−60〜175℃)不良率ともに約0%であったが
、従来の半導体装置では前者が3〜5%、後者が1〜2
%であった。(at -60~175℃) Both defective rates were approximately 0%, but in conventional semiconductor devices, the former was 3~5% and the latter was 1~2%.
%Met.
*+raM錦套あ胛11n売lrゐλn)体Lノ1!−
−督^多結晶シリコンの酸化物の状態で形成されている
ので、そのノ等ツシペーシ四ノ効果によって電流増幅率
を安定にして素子の信頼性及び歩留シを著しく向上させ
ることができる。因みに、実施例の半導体装置20では
、168時間の通電−の前後での電流増幅率の変動は、
第2図に示す如く極めて少ないが、従来の半導体装置で
は同図に併記する通電、通電の前後で電流増幅率が大き
く変化し、不安定であることが確認された。*+raM Nishikimanto 11n sale lrゐλn) body L no 1! −
Since it is formed in the state of polycrystalline silicon oxide, the current amplification factor can be stabilized due to its uniformity effect, and the reliability and yield of the device can be significantly improved. Incidentally, in the semiconductor device 20 of the example, the variation in the current amplification factor before and after 168 hours of energization is as follows.
As shown in FIG. 2, although it is extremely rare, in the conventional semiconductor device, the current amplification factor changes greatly between energization and before and after energization, which is also shown in the same figure, and it has been confirmed that the current amplification factor is unstable.
また、実施例の学導体装置では、歩留シを従来のものに
比べて約1.2倍向上できることが実験的に確認された
。Furthermore, it has been experimentally confirmed that the yield of the conductor device of the example can be improved by about 1.2 times compared to the conventional device.
〔発明の効果〕
以上説明した如く、本発明に係る半導体装置によれば、
配線相互間の層間シ日−ト不良の発生を防止すると共に
、電流増幅率の安定を図って素子の信頼性を向上できる
ものである。[Effects of the Invention] As explained above, according to the semiconductor device according to the present invention,
This prevents the occurrence of interlayer sheet defects between wirings, stabilizes the current amplification factor, and improves the reliability of the device.
第1図は、本発明の一実施例の概略構成を示す説明図、
第2図は、通電後の電流増幅率と通電前の電流増幅率と
の関係を示す特性図である。
1・・・半導体基板、2・・・埋込領域、3・・・Pベ
ース、4・・・Nエミッタ、5・・・絶縁膜、6,7,
9゜11・・・コンタクトホール、8g、8b、8c・
・・第1配線、10・・・層間絶縁膜、12・・・第2
配線、13・・・ノ4ツシペーション膜、20・・・半
導体装置。
出願人代理人 弁理士 鈴 江 武 彦第1図
第2図FIG. 1 is an explanatory diagram showing a schematic configuration of an embodiment of the present invention,
FIG. 2 is a characteristic diagram showing the relationship between the current amplification factor after energization and the current amplification factor before energization. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Buried region, 3... P base, 4... N emitter, 5... Insulating film, 6, 7,
9゜11...Contact hole, 8g, 8b, 8c.
...first wiring, 10...interlayer insulating film, 12...second
Wiring, 13... No. 4 sipation film, 20... Semiconductor device. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2
Claims (1)
、前記能動領域に接続して該半導体基板上に設けられ、
高融点金属またはその合金からなる第1配線と、該第1
配線の周囲を囲むようにして前記半導体基板上に設けら
れた絶縁膜と、前記第1配線を覆うように該絶縁膜上に
設けられ、多結晶シリコンの酸化物からなる層間絶縁膜
と、該層間絶縁膜のコンタクトホールを介して前記第1
配線に接続し、該層間絶縁膜上に設けられた第2配線と
を具備することを特徴とする半導体装置。a semiconductor substrate having an active region constituting a predetermined element; and a semiconductor substrate connected to the active region and provided on the semiconductor substrate,
a first wiring made of a high melting point metal or an alloy thereof;
an insulating film provided on the semiconductor substrate so as to surround the wiring; an interlayer insulating film made of polycrystalline silicon oxide and provided on the insulating film so as to cover the first wiring; and the interlayer insulating film. the first through the contact hole in the film.
A semiconductor device comprising: a second wiring connected to a wiring and provided on the interlayer insulating film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15651185A JPS6218069A (en) | 1985-07-16 | 1985-07-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15651185A JPS6218069A (en) | 1985-07-16 | 1985-07-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6218069A true JPS6218069A (en) | 1987-01-27 |
Family
ID=15629368
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15651185A Pending JPS6218069A (en) | 1985-07-16 | 1985-07-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6218069A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5026256A (en) * | 1987-12-18 | 1991-06-25 | Hitachi, Ltd. | Variable speed pumping-up system |
US5240380A (en) * | 1991-05-21 | 1993-08-31 | Sundstrand Corporation | Variable speed control for centrifugal pumps |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53142196A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Bipolar type semiconductor device |
JPS547864A (en) * | 1977-06-21 | 1979-01-20 | Toshiba Corp | Manufacture for semiconductor device |
JPS55134964A (en) * | 1979-04-10 | 1980-10-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS5637666A (en) * | 1979-09-04 | 1981-04-11 | Toshiba Corp | Semiconductor integrated circuit |
JPS56129342A (en) * | 1980-03-12 | 1981-10-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JPS56146254A (en) * | 1980-04-14 | 1981-11-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS58164241A (en) * | 1982-03-25 | 1983-09-29 | Nec Corp | Manufacture of semiconductor device |
-
1985
- 1985-07-16 JP JP15651185A patent/JPS6218069A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53142196A (en) * | 1977-05-18 | 1978-12-11 | Hitachi Ltd | Bipolar type semiconductor device |
JPS547864A (en) * | 1977-06-21 | 1979-01-20 | Toshiba Corp | Manufacture for semiconductor device |
JPS55134964A (en) * | 1979-04-10 | 1980-10-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
JPS5637666A (en) * | 1979-09-04 | 1981-04-11 | Toshiba Corp | Semiconductor integrated circuit |
JPS56129342A (en) * | 1980-03-12 | 1981-10-09 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JPS56146254A (en) * | 1980-04-14 | 1981-11-13 | Matsushita Electronics Corp | Manufacture of semiconductor device |
JPS58164241A (en) * | 1982-03-25 | 1983-09-29 | Nec Corp | Manufacture of semiconductor device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5026256A (en) * | 1987-12-18 | 1991-06-25 | Hitachi, Ltd. | Variable speed pumping-up system |
US5240380A (en) * | 1991-05-21 | 1993-08-31 | Sundstrand Corporation | Variable speed control for centrifugal pumps |
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