JPS5637666A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS5637666A
JPS5637666A JP11244279A JP11244279A JPS5637666A JP S5637666 A JPS5637666 A JP S5637666A JP 11244279 A JP11244279 A JP 11244279A JP 11244279 A JP11244279 A JP 11244279A JP S5637666 A JPS5637666 A JP S5637666A
Authority
JP
Japan
Prior art keywords
layer
region
type
metallic
diffused
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11244279A
Other languages
Japanese (ja)
Inventor
Minoru Taguchi
Yoshitaka Sasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11244279A priority Critical patent/JPS5637666A/en
Publication of JPS5637666A publication Critical patent/JPS5637666A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE:To enhance the integrating density of a semiconductor integrated circuit by employing a laminate of a metallic layer and a high melting point metallic silicon layer as a first diffused region layer when forming a multilayer wire for an I<2>L, and using an ordinary metallic layer for a second layer making contact partly therewith. CONSTITUTION:An N<+> type buried region 3 is diffused in a P type Si substrate 1, an N type layer 2 is epitaxially grown on the entire surface including the region 3, an N<+> type color layer 4 intruding the periphery of the region 3 is formed, and the layer 2 is partitioned in an island state. A P type injector region 5 and a P type base region 6 are diffused in the layer 2 becoing an island, and an N type collector region 7 is formed in the region 6. Thereafter, an insulating film 8 is coated on the entire surface, and openings are perforated at the respective regions. When a first metallic wiring layer is coated thereon, a laminate of a thin metallic layer 9 made of Pt, Mo, Ta or the like and a metallic layer 10 made of Si compound of MoSi2, W or the like is used. Then, an oxide film 11 is coated thereon as an ordinary method, an opening is perforated thereat, and a second aluminum wiring layer 12 making contact with the laminated on the region 5 is formed thereon.
JP11244279A 1979-09-04 1979-09-04 Semiconductor integrated circuit Pending JPS5637666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11244279A JPS5637666A (en) 1979-09-04 1979-09-04 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11244279A JPS5637666A (en) 1979-09-04 1979-09-04 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5637666A true JPS5637666A (en) 1981-04-11

Family

ID=14586724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11244279A Pending JPS5637666A (en) 1979-09-04 1979-09-04 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5637666A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218069A (en) * 1985-07-16 1987-01-27 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6218069A (en) * 1985-07-16 1987-01-27 Toshiba Corp Semiconductor device

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