JP2845044B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2845044B2 JP2845044B2 JP22908192A JP22908192A JP2845044B2 JP 2845044 B2 JP2845044 B2 JP 2845044B2 JP 22908192 A JP22908192 A JP 22908192A JP 22908192 A JP22908192 A JP 22908192A JP 2845044 B2 JP2845044 B2 JP 2845044B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor device
- insulating film
- polycrystalline silicon
- boundary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係わり、特
にバイポーラトランジスタ等の電極構造を含む集積回路
装置に関する。The present invention relates to a semiconductor device, and more particularly to an integrated circuit device having an electrode structure such as a bipolar transistor.
【０００２】[0002]
【従来の技術】近年半導体装置の高集積化・高速化にと
もない素子寸法の微細化・浅接合化が図られている。2. Description of the Related Art In recent years, as the integration and speed of a semiconductor device have been increased, the element size has been reduced and the junction has been reduced.
【０００３】従来の半導体装置は図６に示すように、一
導電型半導体基板１上にＮ型埋込層２，Ｎ- 型エピタキ
シャル層３ａを設け、酸化シリコン膜４，Ｐ型埋込層６
により周辺素子との絶縁分離がなされている。素子領域
内には選択的にＰ+ 型グラフトベース領域９，Ｐ型活性
ベース領域１０を有している。さらにコレクタ電極部で
は、酸化シリコン膜に選択的に開孔窓を設けてコレクタ
コンタクト領域となるＮ+ 型拡散層３ｂを有している。
また、酸化シリコン膜４に開孔窓を設け活性ベース領域
１０と接続する多結晶シリコン膜７を選択的に設け更に
多結晶シリコン膜よりＮ型不純物原子を導入してＮ型エ
ミッタ領域１４を設けている。エミッタ電極を構成する
多結晶シリコン膜７上全面に層間絶縁膜８を有し、層間
絶縁膜８に選択的に電極窓２７を設けてＮ+ 型拡散層３
ｂの表面、多結晶シリコン膜によるエミッタ電極７の表
面、グラフトベース領域９の表面を露出させ、露出した
シリコン面に高融点金属、例えば白金とシリコンとのシ
リサイド合金膜１９を設けている。更に低導電率の金属
例えばアルミニウム膜を選択的に設けてコレクタ電極２
０−１，エミッタ電極２０−２，ベース電極２０−３を
設けている。A conventional semiconductor device as shown in FIG. 6, N-type buried layer 2 on the one conductivity type semiconductor substrate 1, N - type epitaxial layer 3a is provided, the silicon oxide film 4, P-type buried layer 6
Thereby, insulation isolation from peripheral elements is achieved. In the element region, a P + -type graft base region 9 and a P-type active base region 10 are selectively provided. Further, the collector electrode portion has an N + -type diffusion layer 3b which is provided with an opening window selectively in the silicon oxide film and serves as a collector contact region.
Also, an opening window is provided in the silicon oxide film 4, a polycrystalline silicon film 7 connected to the active base region 10 is selectively provided, and an N-type impurity atom is introduced from the polycrystalline silicon film to provide an N-type emitter region 14. ing. An interlayer insulating film 8 is provided on the entire surface of the polycrystalline silicon film 7 constituting the emitter electrode, and an electrode window 27 is selectively provided in the interlayer insulating film 8 to form an N + type diffusion layer 3.
The surface b, the surface of the emitter electrode 7 made of a polycrystalline silicon film, and the surface of the graft base region 9 are exposed, and a refractory metal, for example, a silicide alloy film 19 of platinum and silicon is provided on the exposed silicon surface. Further, a metal having low conductivity, for example, an aluminum film is selectively provided to form a collector electrode 2.
0-1, an emitter electrode 20-2, and a base electrode 20-3.
【０００４】[0004]
【発明が解決しようとする課題】この従来の半導体装置
では図７（ａ）〜（ｃ）に示す問題点を有している。This conventional semiconductor device has the problems shown in FIGS. 7A to 7C.
【０００５】図７（ａ）に示すエミッタ引き出し電極と
なるＮ型多結晶シリコン膜７は、減圧化学気相成長法に
より多結晶シリコンを被着した後、Ｎ型不純物を添加し
エミッタ領域１４を設けた後、選択的にエッチングして
得られる。しかしエミッタ開孔窓の隣接する側面同志と
底面との交点部にくびれができてしまう。すなわち、酸
化シリコン膜４に形成したエミッタ開孔窓１５によって
Ｎ型多結晶シリコン膜７の表面に段差（凹部）が形成さ
れ、エミッタ開孔窓１５の側面２１と底面２２との境界
線（内角部）２３に対応する多結晶シリコン膜７の表面
端部である境界部分（多結晶シリコン膜の表面段差（凹
部）の内角部）２４にくびれ２５が形成されてしまう。An N-type polycrystalline silicon film 7 serving as an emitter extraction electrode shown in FIG. 7A is formed by depositing polycrystalline silicon by a low pressure chemical vapor deposition method and then adding an N-type impurity to form an emitter region 14. After being provided, it is obtained by selective etching. However, a constriction is formed at the intersection between the adjacent side surfaces and the bottom surface of the emitter aperture window. That is, a step (recess) is formed on the surface of the N-type polycrystalline silicon film 7 by the emitter opening window 15 formed in the silicon oxide film 4, and the boundary line (inner angle) between the side surface 21 and the bottom surface 22 of the emitter opening window 15 is formed. A constriction 25 is formed at a boundary portion (an inner corner portion of a surface step (recess) of the polycrystalline silicon film) which is a surface end of the polycrystalline silicon film 7 corresponding to the portion 23.
【０００６】次にＮ型多結晶シリコン膜７の表面に白金
シリサイドを設ける場合に、図７（ｂ）に示すように白
金１８をスパッタ法により被着した後に５００℃、１０
分程度の熱処理を実施して白金シリサイド膜１９を設
け、未反応白金をエッチング除去し、図７（ｃ）に示す
断面図の状態になる。Next, when providing platinum silicide on the surface of the N-type polycrystalline silicon film 7, as shown in FIG.
The platinum silicide film 19 is provided by performing heat treatment for about a minute, and unreacted platinum is removed by etching, and the state shown in FIG. 7C is obtained.
【０００７】しかしながら前述したくびれ部は白金シリ
サイド１９が特に深く侵入しＰＮ接合領域であるエミッ
タ領域１４に接近し、程度が著しい場合エミッタ領域ま
で達して欠陥を誘起し、トランジスタリークの原因とな
る。However, the constriction described above causes the platinum silicide 19 to penetrate particularly deeply and approach the emitter region 14, which is a PN junction region. If the degree is excessive, the platinum silicide 19 reaches the emitter region to induce defects, thereby causing transistor leakage.
【０００８】特に図７（ｂ）におけるＮ型多結晶シリコ
ン膜７の膜厚と白金１８の膜厚比がおよそ６：１程度よ
り欠陥を誘起しやすくなり、これより白金１８の膜厚の
比率が増加すると欠陥も増加する。In particular, when the ratio of the thickness of the N-type polycrystalline silicon film 7 to the thickness of the platinum 18 in FIG. 7B is about 6: 1, defects are more likely to be induced. As the number increases, so does the number of defects.
【０００９】[0009]
【課題を解決するための手段】本発明の特徴は、半導体
基板上に形成された絶縁層と、前記絶縁層に形成された
開孔窓と、前記開孔窓を覆うように選択的に形成された
不純物を含有せる多結晶シリコン膜と、前記開孔窓下の
半導体基板に形成されたＰＮ接合領域と、前記多結晶シ
リコン膜の表面に形成されたシリサイド合金膜とを有
し、前記多結晶シリコン膜の表面が前記開孔窓によって
段差形状となっている半導体装置に於て、前記開孔窓の
側面と底面との境界線に対応する前記多結晶シリコン膜
の表面段差の底面端部である境界部分に絶縁膜を形成
し、前記多結晶シリコン膜の前記絶縁膜が形成されてい
ない表面の部分に前記シリサイド合金膜が形成されてい
る半導体装置にある。SUMMARY OF THE INVENTION A feature of the present invention is that an insulating layer formed on a semiconductor substrate, an aperture window formed in the insulating layer, and an opening formed selectively to cover the aperture window. A polycrystalline silicon film containing the doped impurity, a PN junction region formed on the semiconductor substrate below the aperture window, and a silicide alloy film formed on the surface of the polycrystalline silicon film. In a semiconductor device in which a surface of a crystalline silicon film has a stepped shape due to the opening window, a bottom end of a surface step of the polycrystalline silicon film corresponding to a boundary between a side surface and a bottom surface of the opening window. In the semiconductor device, an insulating film is formed at a boundary portion, and the silicide alloy film is formed at a surface portion of the polycrystalline silicon film where the insulating film is not formed.
【００１０】[0010]
【実施例】次に本発明について図面を参照して説明す
る。図１は、本発明の第１の実施例の断面図である。Ｐ
型シリコン基板１上にＮ型埋込層２，Ｎ- 型エピタキシ
ャル層３ａが形成され、酸化シリコン膜４およびＰ型埋
込層６により周辺素子と絶縁分離している。さらにコレ
クタ電極部にはコレクタコンタクト領域となるＮ+ 型拡
散層３ｂを有し、Ｐ型活性ベース領域１０，Ｐ+ 型グラ
フトベース領域９を設け、エミッタ開孔窓１５を設け、
選択的に多結晶シリコン膜７を設けてＮ型不純物を添加
してエミッタ領域１４を設け、全面に層間絶縁膜８を設
けてグラフトベース領域９，Ｎ+ 型拡散層３ｂ，Ｎ+ 型
多結晶シリコン膜７上に選択的に電極窓２７を設けるま
では従来と同一構造の為、詳細な説明を省略する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a sectional view of a first embodiment of the present invention. P
An N type buried layer 2 and an N − type epitaxial layer 3 a are formed on a type silicon substrate 1, and are insulated and separated from peripheral elements by a silicon oxide film 4 and a P type buried layer 6. Further, the collector electrode portion has an N + type diffusion layer 3b serving as a collector contact region, a P type active base region 10, a P + type graft base region 9 are provided, and an emitter aperture window 15 is provided.
A polycrystalline silicon film 7 is selectively provided, an N-type impurity is added to provide an emitter region 14, an interlayer insulating film 8 is provided over the entire surface, a graft base region 9, an N + type diffusion layer 3b, and an N + type polycrystal. Until the electrode window 27 is selectively provided on the silicon film 7, the structure is the same as that of the related art, so that the detailed description is omitted.
【００１１】本発明では、次に全面を気相成長法により
酸化シリコン膜を５０乃至２００ｎｍ（ナノメータ）堆
積し、ＣＦ4 等のガスを用いて異方性エッチングして多
結晶シリコン膜の段差（凹部）の側面及び底面部のみに
自己整合的に絶縁膜１２を形成する。In the present invention, next, a silicon oxide film is deposited on the entire surface by a vapor phase growth method to a thickness of 50 to 200 nm (nanometer), and anisotropically etched using a gas such as CF 4 to form a step ( The insulating film 12 is formed only on the side surface and the bottom surface of the concave portion in a self-aligned manner.
【００１２】この時のエミッタ電極部の拡大した断面図
を図１（ｂ）に、平面図を図１（ｃ）に示す。すなわ
ち、酸化シリコン膜４に形成したエミッタ開孔窓１５に
よってＮ型多結晶シリコン膜７の表面に段差（凹部）が
形成され、エミッタ開孔窓１５の側面２１と底面２２と
の境界線（内角部）２３に対応する多結晶シリコン膜７
の表面段差の端部である境界部分（多結晶シリコン膜の
表面段差（凹部）の内角部）２４にのみ自己整合的に酸
化シリコンの絶縁膜１２を設ける。FIG. 1B is an enlarged sectional view of the emitter electrode portion at this time, and FIG. 1C is a plan view thereof. That is, a step (recess) is formed on the surface of the N-type polycrystalline silicon film 7 by the emitter opening window 15 formed in the silicon oxide film 4, and a boundary (inner angle) between the side surface 21 and the bottom surface 22 of the emitter opening window 15 is formed. Part) Polycrystalline silicon film 7 corresponding to 23
The silicon oxide insulating film 12 is provided in a self-aligned manner only at a boundary portion (an inner corner of the surface step (recess) of the polycrystalline silicon film) 24 which is the end of the surface step.
【００１３】その後、ＰＳＧによる層間絶縁膜８を形成
し、そこに電極窓２７を形成し、全面に白金等の高融点
金属を被着し、熱処理により露出する多結晶シリコン膜
７の表面ならびにＰ+ 型グラフトベース９の表面、Ｎ+
型拡散層３ｂの表面にこの高融点金属層とシリコンとの
シリサイド合金膜１９を形成し、層間絶縁膜８上および
本発明の絶縁膜１２上の未反応の高融点金属を除去し、
アルミニウムの金属電極２０−１，乃至２０−３を設け
て図１（ａ）に示す断面図の状態になる。Thereafter, an interlayer insulating film 8 made of PSG is formed, an electrode window 27 is formed thereover, a high melting point metal such as platinum is deposited on the entire surface, and the surface of the polycrystalline silicon film 7 exposed by heat treatment and the P + Type graft base 9 surface, N +
A silicide alloy film 19 of this high melting point metal layer and silicon is formed on the surface of the type diffusion layer 3b, and the unreacted high melting point metal on the interlayer insulating film 8 and the insulating film 12 of the present invention is removed.
When the aluminum metal electrodes 20-1 to 20-3 are provided, the state shown in the sectional view of FIG.
【００１４】本発明によれば、多結晶シリコン膜の表面
凹部の側部と底部の境界部分２４（内角）の個所のくび
れ部に絶縁膜１２を有している為、そこにはシリサイド
合金膜は形成されない。その為シリサイド合金膜が深く
侵入する事はなく半導体装置の歩留りを低下させる事は
ない。According to the present invention, since the insulating film 12 is provided at the constriction at the boundary portion 24 (inner angle) between the side and the bottom of the surface concave portion of the polycrystalline silicon film, the silicide alloy film is provided there. Is not formed. Therefore, the silicide alloy film does not penetrate deeply and the yield of the semiconductor device does not decrease.
【００１５】図２は本発明も第２の実施例を示し、図１
（ｂ）に示す断面図の状態から等方性エッチング処理を
処す事で絶縁膜１２の角部が除去され同図に示すような
テーパー形状を得る事ができる。このようにテーパー状
に絶縁膜を設ける事で後工程で設けた金属電極の被覆性
を向上させる事ができる。従って半導体装置の信頼度を
さらに向上できる。FIG. 2 shows a second embodiment of the present invention.
By performing an isotropic etching process from the state of the cross-sectional view shown in (b), the corners of the insulating film 12 are removed, and a tapered shape as shown in the figure can be obtained. By providing the insulating film in a tapered shape as described above, coverage of the metal electrode provided in a later step can be improved. Therefore, the reliability of the semiconductor device can be further improved.
【００１６】本発明の第３の実施例を示す図３では、前
述した絶縁膜１２を例えば窒化シリコン膜と酸化シリコ
ン膜を積層し、異方性エッチングすると積層膜のエッチ
ング速度の差により窒化シリコン膜３２と酸化シリコン
膜３３による階段状に絶縁膜１２を設ける事ができる。
本実施例は図２と同様に金属電極の被覆性をさらに向上
させる事ができる。In FIG. 3 showing a third embodiment of the present invention, when the above-mentioned insulating film 12 is formed by laminating, for example, a silicon nitride film and a silicon oxide film, and anisotropically etching, the silicon nitride film is formed due to a difference in etching rate of the laminated film. The insulating film 12 can be provided in a stepwise manner by the film 32 and the silicon oxide film 33.
This embodiment can further improve the coverage of the metal electrode as in FIG.
【００１７】図４に示す本発明の第４の実施例では、エ
ミッタ電極部の全面に設けた絶縁膜をフォトリソグラフ
ィ技術を用いて選択的にエミッタ開孔窓上に設けた多結
晶シリコン膜の２辺にのみ設けている。本実施例によれ
ば対向する２辺のみしか絶縁膜１２を設けていない為、
シリサイド合金膜を前述した実施例より広い面積に有す
る事ができエミッタ抵抗を低減できる。従って半導体装
置を高速化を図る事ができる。In the fourth embodiment of the present invention shown in FIG. 4, an insulating film provided on the entire surface of the emitter electrode portion is formed by selectively forming a polycrystalline silicon film on an emitter opening window by using a photolithography technique. It is provided only on two sides. According to the present embodiment, since only the two opposing sides are provided with the insulating film 12,
The silicide alloy film can have a larger area than the above-described embodiment, and the emitter resistance can be reduced. Therefore, the speed of the semiconductor device can be increased.
【００１８】図５に示す本発明の第５の実施例では、エ
ミッタ電極部の平面、は開孔窓１５の４つの側面の角と
底面との境界に対応する多結晶シリコン膜の表面凹部の
境界部分上のみに選択的に絶縁膜１２を設けているか
ら、図４より更にシリサイド合金膜を広い面積に有する
事ができエミッタ抵抗を低減でき高速化を図る事ができ
る。In the fifth embodiment of the present invention shown in FIG. 5, the plane of the emitter electrode portion is formed by the concave portions of the surface of the polycrystalline silicon film corresponding to the boundaries between the corners of the four side surfaces of the aperture window 15 and the bottom surface. Since the insulating film 12 is selectively provided only on the boundary portion, the silicide alloy film can be provided in a wider area than in FIG. 4, and the emitter resistance can be reduced and the speed can be increased.
【００１９】[0019]
【発明の効果】以上説明したように本発明は開孔部を被
覆する多結晶シリコン膜のうち隣接する２つの側面部と
底面部の境界にできたくびれ部に絶縁膜を有し、絶縁膜
を有する領域にシリサイド合金膜を設けていない。As described above, according to the present invention, an insulating film is provided at a narrow portion formed at a boundary between two adjacent side and bottom portions of a polycrystalline silicon film covering an opening. No silicide alloy film is provided in the region having.
【００２０】従ってくびれ部よりシリサイド合金膜が侵
入する事を防止できバイポーラトランジスタのリークを
低減でき、半導体装置を高歩留り化できる。Therefore, it is possible to prevent the silicide alloy film from entering from the constricted portion, to reduce the leakage of the bipolar transistor, and to increase the yield of the semiconductor device.
【図１】本発明の第１の実施例のバイポーラトランジス
タを示す図であり、（ａ）は断面図、（ｂ）は金属電極
を形成する前のエミッタ電極部の拡大断面図、（ｃ）は
（ｂ）の平面図である。FIGS. 1A and 1B are views showing a bipolar transistor according to a first embodiment of the present invention, wherein FIG. 1A is a cross-sectional view, FIG. 1B is an enlarged cross-sectional view of an emitter electrode portion before a metal electrode is formed, and FIG. 4 is a plan view of FIG.
【図２】本発明の第２の実施例の金属電極を形成する前
のエミッタ電極部を拡大して示した断面図である。FIG. 2 is an enlarged sectional view showing an emitter electrode portion before forming a metal electrode according to a second embodiment of the present invention.
【図３】本発明の第３実施例の金属電極を形成する前の
エミッタ電極部を拡大して示した断面図である。FIG. 3 is an enlarged sectional view showing an emitter electrode portion before forming a metal electrode according to a third embodiment of the present invention.
【図４】本発明の第４実施例の金属電極を形成する前の
エミッタ電極部を拡大して示した平面図である。FIG. 4 is an enlarged plan view showing an emitter electrode portion before forming a metal electrode according to a fourth embodiment of the present invention.
【図５】本発明の第５実施例の金属電極を形成する前の
エミッタ電極部を拡大して示した平面図である。FIG. 5 is an enlarged plan view showing an emitter electrode portion before forming a metal electrode according to a fifth embodiment of the present invention.
【図６】従来技術のバイポーラトランジスタを示す断面
図である。FIG. 6 is a sectional view showing a conventional bipolar transistor.
【図７】従来技術の不都合を説明する図であり、エミッ
タ電極部を拡大して示した工程断面図である。FIG. 7 is a view for explaining a disadvantage of the related art, and is a process sectional view showing an emitter electrode portion in an enlarged manner.
１ Ｐ型シリコン基板 ２ Ｎ型埋込層 ３ａ Ｎ- 型エピタキシャル層 ３ｂ Ｎ+ 型拡散層 ４ 酸化シリコン膜 ６ Ｐ型埋込層 ７ Ｎ型多結晶シリコン膜 ８ 層間絶縁層 ９ Ｐ+ 型グラフトベース領域 １０ Ｐ型活性ベース領域 １２，３２，３３ 絶縁膜 １４ Ｎ型エミッタ領域 １５ エミッタ開孔窓 １８ 白金 １９ シリサイド合金膜 ２０−１乃至２０−３ 金属電極 ２１ エミッタ窓の側面 ２２ エミッタ窓の底面 ２３ エミッタ窓の境界線 ２４ 多結晶シリコン膜の表面の境界部分 ２７ 電極窓 Reference Signs List 1 P-type silicon substrate 2 N-type buried layer 3 a N- type epitaxial layer 3 b N + -type diffusion layer 4 silicon oxide film 6 P-type buried layer 7 N-type polycrystalline silicon film 8 interlayer insulating layer 9 P + -type graft base Region 10 P-type active base region 12, 32, 33 Insulating film 14 N-type emitter region 15 Emitter opening window 18 Platinum 19 Silicide alloy film 20-1 to 20-3 Metal electrode 21 Side surface of emitter window 22 Bottom surface of emitter window 23 Boundary line of emitter window 24 Boundary part of surface of polycrystalline silicon film 27 Electrode window
フロントページの続き (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/33 - 21/331 H01L 29/68 - 29/737 H01L 21/28 - 21/288 H01L 21/44 - 21/445 H01L 29/40 - 29/43 H01L 29/47 H01L 29/872Continued on the front page (58) Fields surveyed (Int.Cl. 6 , DB name) H01L 21/33-21/331 H01L 29/68-29/737 H01L 21/28-21/288 H01L 21/44-21 / 445 H01L 29/40-29/43 H01L 29/47 H01L 29/872
Claims (10)
記絶縁層に形成された開孔窓と、前記開孔窓を覆うよう
に選択的に形成された不純物を含有せる多結晶シリコン
膜と、前記開孔窓下の半導体基板に形成されたＰＮ接合
領域と、前記多結晶シリコン膜の表面に形成されたシリ
サイド合金膜とを有し、前記多結晶シリコン膜の表面が
前記開孔窓によって段差形状となっている半導体装置に
於て、前記開孔窓の側面と底面との境界線に対応する前
記多結晶シリコン膜の表面段差の底面端部である境界部
分に絶縁膜を形成し、前記多結晶シリコン膜の前記絶縁
膜が形成されていない表面の部分に前記シリサイド合金
膜が形成されていることを特徴とする半導体装置。1. An insulating layer formed on a semiconductor substrate, an aperture window formed in the insulating layer, and a polycrystalline silicon film containing impurities selectively formed to cover the aperture window. And a PN junction region formed on the semiconductor substrate below the aperture window, and a silicide alloy film formed on the surface of the polycrystalline silicon film, wherein the surface of the polycrystalline silicon film is the aperture window. In the semiconductor device having a stepped shape, an insulating film is formed at a boundary portion which is a bottom end portion of a surface step of the polycrystalline silicon film corresponding to a boundary line between a side surface and a bottom surface of the opening window. A semiconductor device, wherein the silicide alloy film is formed in a portion of the surface of the polycrystalline silicon film where the insulating film is not formed.
に対応する前記多結晶シリコン膜表面の前記境界部分に
前記絶縁膜が形成されていることを特徴とする請求項１
に記載の半導体装置。2. The insulating film is formed on the boundary portion of the surface of the polycrystalline silicon film corresponding to the entire boundary between all side surfaces and the bottom surface of the aperture window.
3. The semiconductor device according to claim 1.
との境界線に対応する前記多結晶シリコン膜表面の前記
境界部分のみに前記絶縁膜が形成されていることを特徴
とする請求項１に記載の半導体装置。3. The insulating film is formed only on the boundary portion of the surface of the polycrystalline silicon film corresponding to the boundary between two opposing side surfaces and the bottom surface of the aperture window. Item 2. The semiconductor device according to item 1.
境界に対応する前記多結晶シリコン膜表面の前記境界部
分のみに前記絶縁膜が形成されていることを特徴とする
請求項１に記載の半導体装置。4. The insulating film is formed only on the boundary portion of the surface of the polycrystalline silicon film corresponding to the boundary between the corner and the bottom surface of the two side surfaces of the aperture window. 2. The semiconductor device according to 1.
とを特徴とする請求項１に記載の半導体装置。5. The semiconductor device according to claim 1, wherein said insulating film has a tapered cross-sectional shape.
特徴とする請求項１に記載の半導体装置。6. The semiconductor device according to claim 1, wherein said insulating film has a rectangular cross-sectional shape.
断面形状から成る階段状の断面形状であることを特徴と
する請求項１に記載の半導体装置。7. The semiconductor device according to claim 1, wherein the insulating film has a step-like cross-sectional shape including a plurality of rectangular cross-sectional shapes having different sizes.
れていることを特徴とする請求項１乃至請求項７に記載
の半導体装置。8. The semiconductor device according to claim 1, wherein said insulating film comprises a silicon oxide film.
れていることを特徴とする請求項１乃至請求項７に記載
の半導体装置。9. The semiconductor device according to claim 1, wherein said insulating film is made of a silicon nitride film.
リコン膜を複数積層した積層膜から構成されていること
を特徴とする請求項１乃至請求項７に記載の半導体装
置。10. The semiconductor device according to claim 1, wherein said insulating film is formed of a stacked film in which a plurality of silicon oxide films and silicon nitride films are stacked.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22908192A JP2845044B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22908192A JP2845044B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0677240A JPH0677240A (en) | 1994-03-18 |
| JP2845044B2 true JP2845044B2 (en) | 1999-01-13 |
Family
ID=16886455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22908192A Expired - Lifetime JP2845044B2 (en) | 1992-08-28 | 1992-08-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2845044B2 (en) |
-
1992
- 1992-08-28 JP JP22908192A patent/JP2845044B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0677240A (en) | 1994-03-18 |
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