JPS6127178U - display device - Google Patents

display device

Info

Publication number
JPS6127178U
JPS6127178U JP11061984U JP11061984U JPS6127178U JP S6127178 U JPS6127178 U JP S6127178U JP 11061984 U JP11061984 U JP 11061984U JP 11061984 U JP11061984 U JP 11061984U JP S6127178 U JPS6127178 U JP S6127178U
Authority
JP
Japan
Prior art keywords
display device
gate lines
parallel
drain
lines arranged
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11061984U
Other languages
Japanese (ja)
Other versions
JPH0345216Y2 (en
Inventor
平 波田
Original Assignee
三洋電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 三洋電機株式会社 filed Critical 三洋電機株式会社
Priority to JP11061984U priority Critical patent/JPS6127178U/en
Publication of JPS6127178U publication Critical patent/JPS6127178U/en
Application granted granted Critical
Publication of JPH0345216Y2 publication Critical patent/JPH0345216Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Testing Electric Properties And Detecting Electric Faults (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の表示装置の要部を示す平面図、第2図
aは従来の表示装置の平面図、同図bはそのX−X線断
面図を示す。 13・・・アモノレファスシリコン’層、14・・・ド
レインライン、15・・・ソースiEi、16−・・ゲ
ートライン。
FIG. 1 is a plan view showing essential parts of the display device of the present invention, FIG. 2a is a plan view of a conventional display device, and FIG. 13--Amono-rephasic silicon layer, 14--Drain line, 15--Source iEi, 16--Gate line.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 並列配置された複数本のゲートラインと、該ゲートライ
ン上に層間絶縁膜を介して並列配置された複数本のドレ
インラインとが交差し、このマトリクス状の各交差点に
てFETからなるスイッチングトランジスタのソース側
に表示セグメント電極を結合した表示装置に於いて、上
記ドレインライン又はゲートラインの形状を一定本数の
間隔をもって周期的に異ならしめた事を特徴とする表示
装置。
A plurality of gate lines arranged in parallel intersect with a plurality of drain lines arranged in parallel on the gate lines via an interlayer insulating film, and at each intersection of this matrix, a switching transistor consisting of an FET is connected. 1. A display device in which a display segment electrode is coupled to a source side, characterized in that the shapes of the drain lines or gate lines are periodically varied at intervals of a certain number.
JP11061984U 1984-07-20 1984-07-20 display device Granted JPS6127178U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11061984U JPS6127178U (en) 1984-07-20 1984-07-20 display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11061984U JPS6127178U (en) 1984-07-20 1984-07-20 display device

Publications (2)

Publication Number Publication Date
JPS6127178U true JPS6127178U (en) 1986-02-18
JPH0345216Y2 JPH0345216Y2 (en) 1991-09-25

Family

ID=30669743

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11061984U Granted JPS6127178U (en) 1984-07-20 1984-07-20 display device

Country Status (1)

Country Link
JP (1) JPS6127178U (en)

Also Published As

Publication number Publication date
JPH0345216Y2 (en) 1991-09-25

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