JPS6092281U - Thin film transistor substrate for liquid crystal display devices - Google Patents
Thin film transistor substrate for liquid crystal display devicesInfo
- Publication number
- JPS6092281U JPS6092281U JP18543783U JP18543783U JPS6092281U JP S6092281 U JPS6092281 U JP S6092281U JP 18543783 U JP18543783 U JP 18543783U JP 18543783 U JP18543783 U JP 18543783U JP S6092281 U JPS6092281 U JP S6092281U
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- film transistor
- liquid crystal
- crystal display
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例を示す平面図、第2図はそのA−A線断
面図、第3図は特性図、第4図はこの考案の一実施例を
示す断面図である。
1・・・ゲート線、2・・・ソース線、3・・・アモル
ファスシリコン、4・・・薄膜トランジスタ、5・・・
ゲート電極、9・・・基板、10・・・基板被覆用絶縁
層、11・・・ゲート用絶縁層。FIG. 1 is a plan view showing a conventional example, FIG. 2 is a sectional view taken along the line A--A, FIG. 3 is a characteristic diagram, and FIG. 4 is a sectional view showing an embodiment of this invention. 1... Gate line, 2... Source line, 3... Amorphous silicon, 4... Thin film transistor, 5...
Gate electrode, 9... Substrate, 10... Insulating layer for covering substrate, 11... Insulating layer for gate.
Claims (1)
その交点付近にアモルファスシリコンを半導体層とする
薄膜トランジスタ婆形成した基板と、透明電極を形成し
た基板との間に液晶を挟持させてなるアクティブマトリ
ックス型の液晶表示装置において、前記ゲート線・ソー
ス線間の絶縁層を基板被覆用絶縁層と薄膜トランジスタ
のゲート用絶縁層との2層により形成したことを特徴と
する液晶表示装置用薄膜トランジスタ基板。A liquid crystal is sandwiched between a substrate having a plurality of gate lines and source lines orthogonal to each other and a thin film transistor formed with amorphous silicon as a semiconductor layer near the intersection thereof, and a substrate having a transparent electrode formed thereon. 1. A thin film transistor substrate for a matrix type liquid crystal display device, wherein the insulating layer between the gate line and the source line is formed of two layers: a substrate covering insulating layer and a gate insulating layer of the thin film transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18543783U JPS6092281U (en) | 1983-11-30 | 1983-11-30 | Thin film transistor substrate for liquid crystal display devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP18543783U JPS6092281U (en) | 1983-11-30 | 1983-11-30 | Thin film transistor substrate for liquid crystal display devices |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6092281U true JPS6092281U (en) | 1985-06-24 |
JPH0417929Y2 JPH0417929Y2 (en) | 1992-04-22 |
Family
ID=30400804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP18543783U Granted JPS6092281U (en) | 1983-11-30 | 1983-11-30 | Thin film transistor substrate for liquid crystal display devices |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6092281U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61145582A (en) * | 1984-12-20 | 1986-07-03 | キヤノン株式会社 | Display unit |
-
1983
- 1983-11-30 JP JP18543783U patent/JPS6092281U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61145582A (en) * | 1984-12-20 | 1986-07-03 | キヤノン株式会社 | Display unit |
Also Published As
Publication number | Publication date |
---|---|
JPH0417929Y2 (en) | 1992-04-22 |
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