JPH0244722U - - Google Patents
Info
- Publication number
- JPH0244722U JPH0244722U JP12290688U JP12290688U JPH0244722U JP H0244722 U JPH0244722 U JP H0244722U JP 12290688 U JP12290688 U JP 12290688U JP 12290688 U JP12290688 U JP 12290688U JP H0244722 U JPH0244722 U JP H0244722U
- Authority
- JP
- Japan
- Prior art keywords
- bus line
- tft
- insulating substrate
- gate bus
- drain bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims 1
- 239000010409 thin film Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Liquid Crystal Display Device Control (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Thin Film Transistor (AREA)
Description
第1図は本考案のTFTマトリクスアレイのド
レイン端子の断面図、第2図は本考案のTFTマ
トリクスアレイのドレイン端子の平面図、第3図
はTFTパネルの模式図である。
1…端子電極、2…ドレインバスライン、3…
層間絶縁膜、4…ガラス基板、5…コンタクトホ
ール。
FIG. 1 is a sectional view of the drain terminal of the TFT matrix array of the present invention, FIG. 2 is a plan view of the drain terminal of the TFT matrix array of the present invention, and FIG. 3 is a schematic diagram of the TFT panel. 1...Terminal electrode, 2...Drain bus line, 3...
Interlayer insulating film, 4... glass substrate, 5... contact hole.
Claims (1)
)をマトリクス配置し、該TFTの配線電極であ
るゲートバスライン又はドレインバスラインと絶
縁基板周辺位置に設けたゲートバスライン用端子
又はドレインバスライン端子とを絶縁膜のコンタ
クトホールを介して接続した端子構造を有するT
FTマトリクスアレイに於いて、上記コンタクト
ホールを数字パターンで形成したことを特徴とし
たTFTマトリクスアレイ。 A plurality of TFTs (thin film transistors) are arranged in a matrix on an insulating substrate, and the gate bus line or drain bus line, which is the wiring electrode of the TFT, is insulated from the gate bus line terminal or drain bus line terminal provided around the insulating substrate. T having a terminal structure connected through a contact hole in the membrane
A TFT matrix array characterized in that the contact holes are formed in a numerical pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988122906U JPH071676Y2 (en) | 1988-09-20 | 1988-09-20 | TFT matrix array |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988122906U JPH071676Y2 (en) | 1988-09-20 | 1988-09-20 | TFT matrix array |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0244722U true JPH0244722U (en) | 1990-03-28 |
JPH071676Y2 JPH071676Y2 (en) | 1995-01-18 |
Family
ID=31371277
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988122906U Expired - Lifetime JPH071676Y2 (en) | 1988-09-20 | 1988-09-20 | TFT matrix array |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH071676Y2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002108241A (en) * | 2000-10-03 | 2002-04-10 | Fujitsu Ltd | Active matrix type display device and manufacturing method therefor |
JP2004126597A (en) * | 2003-10-06 | 2004-04-22 | Seiko Epson Corp | Substrate for liquid crystal panel and liquid crystal panel using the same and projection type display |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62120732U (en) * | 1986-01-21 | 1987-07-31 |
-
1988
- 1988-09-20 JP JP1988122906U patent/JPH071676Y2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62120732U (en) * | 1986-01-21 | 1987-07-31 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002108241A (en) * | 2000-10-03 | 2002-04-10 | Fujitsu Ltd | Active matrix type display device and manufacturing method therefor |
JP4566377B2 (en) * | 2000-10-03 | 2010-10-20 | シャープ株式会社 | Active matrix display device and manufacturing method thereof |
JP2004126597A (en) * | 2003-10-06 | 2004-04-22 | Seiko Epson Corp | Substrate for liquid crystal panel and liquid crystal panel using the same and projection type display |
Also Published As
Publication number | Publication date |
---|---|
JPH071676Y2 (en) | 1995-01-18 |
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