JPS6119136A - Wire-bonding method for semiconductor device and bonding pad to be used for that - Google Patents

Wire-bonding method for semiconductor device and bonding pad to be used for that

Info

Publication number
JPS6119136A
JPS6119136A JP59139337A JP13933784A JPS6119136A JP S6119136 A JPS6119136 A JP S6119136A JP 59139337 A JP59139337 A JP 59139337A JP 13933784 A JP13933784 A JP 13933784A JP S6119136 A JPS6119136 A JP S6119136A
Authority
JP
Japan
Prior art keywords
bonding
bonding pad
pad
parts
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59139337A
Other languages
Japanese (ja)
Inventor
Kazuhide Sato
和秀 佐藤
Akira Kuromaru
黒丸　明
Seiichi Hirata
誠一 平田
Koichiro Atsumi
幸一郎 渥美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59139337A priority Critical patent/JPS6119136A/en
Publication of JPS6119136A publication Critical patent/JPS6119136A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4807—Shape of bonding interfaces, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4845—Details of ball bonds
    • H01L2224/48451—Shape
    • H01L2224/48453—Shape of the interface with the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To relax stress to be applied to the bonding pad provided on a semiconductor pellet at the time of wire-bonding and to prevent any crack from generating by a method wherein notch parts, grooves, apertures and so forth are formed in advance on the bonding pad by performing an etching. CONSTITUTION:An SiO2 layer 7 is adhered on an Si substrate 6 and a bonding pad 1 is provided thereon. When a bonding wire 8 is fushion welded on the bonding pad 1, opening parts to pierce the pad 1 through or opening parts to stop on the way are formed in advance on the pad 1. At this time, the opening parts are constituted being carved notch parts 2, notch parts 3 and grooves 4 tereon, or being provided apertures 5 and so forth thereon. In such a constitution, as the generation of cracks due to stress strain is mainly generated on the circumferential edge parts of the holes of the pad 1, roughened notch parts 2 are provided on the circumferential edge parts of the holes of the pad 1, or notch parts 3 are formed on the corner parts of the holes of the pad 1. Or, apertures 5 are specially provided on the corner parts. By such a way, the pad itself is made to hold the function of stress relaxation. As a result, the generation of the cracks can be prevented.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は半導体装置のワイヤボンディング、特にボンデ
ィング時の応力を緩和させるようなワイヤボンディング
方法およびボンディングパッドに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to wire bonding of semiconductor devices, and more particularly to a wire bonding method and bonding pad that relieve stress during bonding.

（発明の技術的背景） 半導体ペレット上の各素子をインナーリードと電気的に
接続するためのワイヤボンディングは、通常、半導体ベ
レット上に正方形のボンディングパッドを形成し、この
ボンディングパッドにボンディングワイヤをボンディン
グすることによって行われる。一般にこのボンディング
パッドはｓｉｏ、、上に設けられたＡＩ、Ａｕ等の金属
で、ボンディングワイヤにもＡＩ、Ａｕ等の金属が用い
られている。ボンディングは、ボンディングワイヤの先
端をボール状にし、ボンディングパッドに４０〜６０ｇ
の荷重をかけて接触させ、３５０℃程度の温度で熱圧着
させるのが一般的である。また、最近では圧力と熱の他
に、超音波による振動を加える方法も行われており、こ
の方法では２５０℃程度の温度でボンディングが可能で
ある。(Technical Background of the Invention) Wire bonding for electrically connecting each element on a semiconductor pellet to an inner lead usually involves forming a square bonding pad on the semiconductor pellet and bonding a bonding wire to this bonding pad. It is done by doing. Generally, this bonding pad is made of a metal such as AI or Au provided on the sio, and the bonding wire is also made of a metal such as AI or Au. For bonding, make the tip of the bonding wire into a ball shape and apply 40 to 60 g to the bonding pad.
It is common to bring them into contact by applying a load of 300° C., and to bond them under heat and pressure at a temperature of about 350° C. Furthermore, in addition to pressure and heat, a method of applying ultrasonic vibration has recently been used, and with this method, bonding can be performed at a temperature of about 250°C.

〔前頭技術の問題点〕 上述のようにワイヤボンディングは一般に圧力、熱、振
動を加えるため、ワイヤボンディング時の応力歪みによ
り、ボンディングパッドの下地となるＳｔＯ，、等の絶
縁層、更にはその下のシリコン層にまでクラックが生じ
ることがある。このようなりラックはリーク電流を誘引
する原因となり、また、素子領域にボンディングパッド
が配置されている場合には、素子自体が破壊されること
になる。このようなりラックの発生をおさえる主な手段
として以下の４つの方法があるが、いずれもそれぞれ欠
点をもっている。[Problems with frontal technology] As mentioned above, wire bonding generally applies pressure, heat, and vibration, and stress strain during wire bonding can damage the insulating layer such as StO, which is the base of the bonding pad, and even the underlying layer. Cracks may occur even in the silicon layer. This rack causes leakage current, and if bonding pads are arranged in the element region, the element itself will be destroyed. There are four main methods for suppressing the occurrence of racks, but each method has its own drawbacks.

まず第１の方法はボンディングパッド面積を増大さぜで
やる方法である。圧力が広範囲に分散するため単位面積
あたりの応力は小さくなる。しかし近年ＶＬＳＩ等の高
集積化が進んでおり、ボンディングパッドの大きさを増
大させることは、この高集積化技術に逆行し好ましくな
い。The first method is to increase the bonding pad area. Since the pressure is dispersed over a wide range, the stress per unit area becomes small. However, in recent years, VLSI and other devices have become highly integrated, and increasing the size of bonding pads is undesirable because it goes against this high integration technology.

第２の方法はボンディング速度を遅くしてやる方法であ
る。ボンディングワイヤをボンディングパッドに接触さ
せる加速度を小さくすれば、それだけ動的荷重が減り、
加わる応力も減少する。しかし近年半導体素子の需要が
急速に増大し、また、１チツプあたりの端子数増大を考
えると、生産工程の速度を遅延させる方法は好ましくな
い。The second method is to slow down the bonding speed. If you reduce the acceleration that brings the bonding wire into contact with the bonding pad, the dynamic load will decrease accordingly.
The applied stress is also reduced. However, in view of the rapid increase in demand for semiconductor devices in recent years and the increase in the number of terminals per chip, methods that slow down the production process are not desirable.

第３の方法はボンディングパッドの厚みに比較して、そ
の下地となる絶縁層の厚みを厚くしてやる方法である。The third method is to increase the thickness of the underlying insulating layer compared to the thickness of the bonding pad.

熱に起因するクラックは、主として熱膨張率の相違によ
るものである。例えばＡｌｄｅｇ　〕のオーダである。Cracks caused by heat are mainly due to differences in thermal expansion coefficients. For example, the order is [Aldeg].

従ってボンディング後の冷却時に５ｈｏ２層とＡ１層と
の間に応力歪みを生じクラックが発生する原因となる。Therefore, during cooling after bonding, stress strain occurs between the 5ho2 layer and the A1 layer, causing cracks to occur.

そこで５ｈｏ２層の厚みをＡ１層の厚みに比べて十分厚
くしてやれば応力分散が図れる。しかし、Ｓ　ｉ　０２
層の厚みを増大させることはチップサイズの増大、生産
工程時間の増大につながり好ましくない。Therefore, if the thickness of the 5ho2 layer is made sufficiently thicker than the thickness of the A1 layer, stress distribution can be achieved. However, S i 02
Increasing the layer thickness is undesirable because it leads to an increase in chip size and production process time.

第４の方法はボンディングパッドの下地となる層にポリ
シリコン層等の衝撃緩和層を設ける方法である。しかし
この方法は、生産工程の増加、生産コストの増加を招き
好ましくない。A fourth method is to provide a shock absorbing layer such as a polysilicon layer on the layer underlying the bonding pad. However, this method is undesirable because it increases the number of production steps and production costs.

〔発明の目的〕[Purpose of the invention]

そこで本発明は集積度、ボンディング速度を低下させる
ことなく、簡易な工程でクラックの発生を防ぐことので
きる半導体装置のワイヤボンディング方法およびこれに
用いるボンディングパッドを提供することを目的とする
。SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a wire bonding method for a semiconductor device that can prevent the occurrence of cracks in a simple process without reducing the degree of integration or bonding speed, and a bonding pad used in the method.

〔発明の概要〕[Summary of the invention]

本発明の特徴は、ボンディングパッドに、ワイヤボンデ
ィング時に加わる応力を緩和するための切欠き部、溝、
または開口部を設けてワイヤボンディングを付い、クラ
ックの発生を防止したことにある。A feature of the present invention is that the bonding pad has notches and grooves for relieving stress applied during wire bonding.
Another method is to provide an opening and attach wire bonding to prevent the occurrence of cracks.

〔発明の実加例〕[Example of practical application of invention]

以下本発明を図示する実施例に基づいて説明する。第１
図（ａ）、（ｂ）は切欠き部、同（Ｃ）は溝、同（（１
）は開口部をそれぞれボンディングパッド１に設けた実
施例である。第１図（ａ）はボンディングパッド１の周
縁の輪郭が凹凸をなすように切欠き部２を設けたもので
ある。応力歪みによるクラックは主にボンディングパッ
ドの周縁部に生ずるため、周縁部にこのような切欠き部
を設けることはきわめて効果的である。１１図（ｂ）は
ボンデインクバッド１の隅部に切欠き部３を設けたもの
であ−る。一般に正方形のボンディングパッドの場合、
隅部に応力が集中するため、このような切欠き部３も応
力分散に有効に作用する。第１図（Ｃ）はボンディング
パッド１に溝４を設けた例である。応力歪みはボンディ
ングパッド１の中心から周囲に向けて生じるため、この
溝４はボンディングパッド１の周縁の輪郭とほぼ相似形
をなすように形成１゛るのが好ましい。第１図（ｄ）は
ボンディングパッド１の周縁部に開口部５を設けだもの
である。前述の理由から開口部５は周縁部、特に隅部に
設けるのが最も効果的である。The present invention will be described below based on illustrated embodiments. 1st
Figures (a) and (b) are notches, (C) are grooves, and ((1)
) is an embodiment in which openings are provided in the bonding pads 1, respectively. In FIG. 1(a), a notch 2 is provided so that the outline of the periphery of the bonding pad 1 is uneven. Since cracks due to stress strain mainly occur at the periphery of the bonding pad, providing such a notch at the periphery is extremely effective. FIG. 11(b) shows a bonded ink pad 1 in which a notch 3 is provided at the corner. Generally, for square bonding pads,
Since stress is concentrated at the corners, such a notch 3 also effectively acts to disperse stress. FIG. 1C shows an example in which a groove 4 is provided in the bonding pad 1. Since stress strain occurs from the center of the bonding pad 1 toward the periphery, it is preferable that the groove 4 is formed so as to have a substantially similar shape to the contour of the periphery of the bonding pad 1. In FIG. 1(d), an opening 5 is provided at the periphery of the bonding pad 1. For the reasons mentioned above, it is most effective to provide the openings 5 at the periphery, especially at the corners.

第２図は第１図（ｄ）に示す実施例のボンディング状態
を示す断面図である。シリコン基板６の上にＳｉＯ□層
７が形成され、その上にボンディングパッド１が形成さ
れる。開口部５は第２図（ａ）に示すようにボンディン
グパッド１を貫くように形成してもよく、また第２図（
ｂ）に示すようにボンディングパッド１の厚みより浅く
形成してもよい。前者の場合は、応力緩和機能は向上す
るが、ボンディング力は弱まる。後者の場合はこれと逆
になる。ボンディングワイヤ８は従来と同様に圧力、熱
振動が加えられてボンディングパッド１に熱圧着される
。FIG. 2 is a sectional view showing the bonding state of the embodiment shown in FIG. 1(d). A SiO□ layer 7 is formed on a silicon substrate 6, and a bonding pad 1 is formed thereon. The opening 5 may be formed to penetrate the bonding pad 1 as shown in FIG.
As shown in b), it may be formed to be shallower than the thickness of the bonding pad 1. In the former case, the stress relaxation function is improved, but the bonding force is weakened. In the latter case, the opposite is true. The bonding wire 8 is thermocompression bonded to the bonding pad 1 by applying pressure and thermal vibration as in the conventional case.

〔発明の効果〕〔Effect of the invention〕

以上のとおり本発明によれば、ボンディングパッドに、
ワイヤボンディング時に加わる応力を緩和するための切
欠き部、溝、または開口部を設け、ボンディングパッド
自体に応力緩和機能をもたせるようにしたため、集積度
、ボンディング速僚を低下させることなく、簡易な工程
でワイヤボンディング時のクラックの発生を防止するこ
とができ、また、半導体素子領域にボンディングパッド
を設けることも可能となる。As described above, according to the present invention, the bonding pad includes
Notches, grooves, or openings are provided to relieve the stress applied during wire bonding, and the bonding pad itself has a stress-relieving function, which simplifies the process without reducing the degree of integration or bonding speed. This makes it possible to prevent cracks from occurring during wire bonding, and it also becomes possible to provide bonding pads in the semiconductor element region.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明に係るボンディングパッドの上面図、第
２図は本発明に係るボンディングパッドの縦断面図であ
る。 １・・・ボンディングパッド、２．３・・・切欠き部、
４・・・漏、５・・・開口部、６・・・シリコン基板、
７・・・Ｓ　ｉ　Ｏ２層、８・・・ボンディングワイヤ
。 ６１　圀 （ａ）　　　　　　（ｂ）　　　　　（Ｃ）　　　　　
（ｄ）色２　図FIG. 1 is a top view of a bonding pad according to the present invention, and FIG. 2 is a longitudinal sectional view of the bonding pad according to the present invention. 1... Bonding pad, 2.3... Notch,
4...Leakage, 5...Opening, 6...Silicon substrate,
7...S i O2 layer, 8... Bonding wire. 61 Country (a) (b) (C)
(d) Color 2 Figure

Claims (1)

【特許請求の範囲】 １、半導体ペレットにボンディングパッドを形成し、前
記ボンディングパッドに、ワイヤボンディング時に加わ
る応力を緩和するための切欠き部、溝、または開口部を
設け、ボンディングワイヤを前記ボンディングパッドに
ボンディングすることを特徴とする半導体装置のワイヤ
ボンディング方法。 ２、切欠き部、溝、または開口部をエッチングにより設
けることを特徴とする特許請求の範囲第１項記載の半導
体装置のワイヤボンディング方法。 ３、ワイヤボンディング時に加わる応力を緩和するため
の切欠き部、溝、または開口部を有することを特徴とす
るボンディングパッド。 ４、周縁の輪郭が凹凸をなすように切欠き部を形成した
ことを特徴とする特許請求の範囲第３項記載のボンディ
ングパッド。 ５、隅部に切欠き部を形成したことを特徴とする特許請
求の範囲第３項記載のボンディングパッド。 ６、周縁の輪郭とほぼ相似形をなすように溝を形成した
ことを特徴とする特許請求の範囲第３項記載のボンディ
ングパッド。 ７、周縁部に開口部を形成したことを特徴とする特許請
求の範囲第３項記載のボンディングパッド。 ８、開口部の深さがボンディングパッドの厚みに等しい
ことを特徴とする特許請求の範囲第３項目または第７項
記載のボンディングパッド。 ９、開口部の深さがボンディングパッドの厚みより小さ
いことを特徴とする特許請求の範囲第３項目または第７
項記載のボンディングパッド。[Claims] 1. A bonding pad is formed on a semiconductor pellet, a notch, a groove, or an opening is provided in the bonding pad to relieve stress applied during wire bonding, and a bonding wire is attached to the bonding pad. 1. A wire bonding method for a semiconductor device, characterized by bonding to a semiconductor device. 2. The wire bonding method for a semiconductor device according to claim 1, wherein the notch, groove, or opening is provided by etching. 3. A bonding pad characterized by having a notch, groove, or opening for relieving stress applied during wire bonding. 4. The bonding pad according to claim 3, wherein the notch portion is formed so that the contour of the periphery is uneven. 5. The bonding pad according to claim 3, characterized in that a notch is formed at a corner. 6. The bonding pad according to claim 3, wherein the groove is formed to have a shape substantially similar to the contour of the peripheral edge. 7. The bonding pad according to claim 3, characterized in that an opening is formed in the peripheral edge. 8. The bonding pad according to claim 3 or 7, wherein the depth of the opening is equal to the thickness of the bonding pad. 9. Claim 3 or 7, characterized in that the depth of the opening is smaller than the thickness of the bonding pad.
Bonding pad as described in section.
JP59139337A 1984-07-05 1984-07-05 Wire-bonding method for semiconductor device and bonding pad to be used for that Pending JPS6119136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59139337A JPS6119136A (en) 1984-07-05 1984-07-05 Wire-bonding method for semiconductor device and bonding pad to be used for that

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59139337A JPS6119136A (en) 1984-07-05 1984-07-05 Wire-bonding method for semiconductor device and bonding pad to be used for that

Publications (1)

Publication Number Publication Date
JPS6119136A true JPS6119136A (en) 1986-01-28

Family

ID=15242973

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59139337A Pending JPS6119136A (en) 1984-07-05 1984-07-05 Wire-bonding method for semiconductor device and bonding pad to be used for that

Country Status (1)

Country Link
JP (1) JPS6119136A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
US5194931A (en) * 1989-06-13 1993-03-16 Kabushiki Kaisha Toshiba Master slice semiconductor device
EP0897215A3 (en) * 1997-08-11 2000-08-09 Murata Manufacturing Co., Ltd. Surface acoustic wave device
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
JP2004247659A (en) * 2003-02-17 2004-09-02 Elpida Memory Inc Semiconductor device
KR100570239B1 (en) * 1997-02-27 2006-07-25 산요덴키가부시키가이샤 Semiconductor device and manufacturing method for semiconductor device
JP2012119712A (en) * 2006-10-31 2012-06-21 Cree Inc Integrated heat spreaders for leds and related assemblies
JPWO2012073302A1 (en) * 2010-11-29 2014-05-19 トヨタ自動車株式会社 Semiconductor device
WO2014157458A1 (en) * 2013-03-29 2014-10-02 住友大阪セメント株式会社 Optical waveguide element

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4959706A (en) * 1988-05-23 1990-09-25 United Technologies Corporation Integrated circuit having an improved bond pad
US5194931A (en) * 1989-06-13 1993-03-16 Kabushiki Kaisha Toshiba Master slice semiconductor device
KR100570239B1 (en) * 1997-02-27 2006-07-25 산요덴키가부시키가이샤 Semiconductor device and manufacturing method for semiconductor device
EP0897215A3 (en) * 1997-08-11 2000-08-09 Murata Manufacturing Co., Ltd. Surface acoustic wave device
US6365978B1 (en) * 1999-04-02 2002-04-02 Texas Instruments Incorporated Electrical redundancy for improved mechanical reliability in ball grid array packages
JP2004247659A (en) * 2003-02-17 2004-09-02 Elpida Memory Inc Semiconductor device
JP2012119712A (en) * 2006-10-31 2012-06-21 Cree Inc Integrated heat spreaders for leds and related assemblies
JPWO2012073302A1 (en) * 2010-11-29 2014-05-19 トヨタ自動車株式会社 Semiconductor device
US8836150B2 (en) 2010-11-29 2014-09-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device
WO2014157458A1 (en) * 2013-03-29 2014-10-02 住友大阪セメント株式会社 Optical waveguide element
JP2014199339A (en) * 2013-03-29 2014-10-23 住友大阪セメント株式会社 Optical waveguide element

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