JPH1074778A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH1074778A
JPH1074778A JP8228736A JP22873696A JPH1074778A JP H1074778 A JPH1074778 A JP H1074778A JP 8228736 A JP8228736 A JP 8228736A JP 22873696 A JP22873696 A JP 22873696A JP H1074778 A JPH1074778 A JP H1074778A
Authority
JP
Japan
Prior art keywords
semiconductor chip
island
semiconductor device
semiconductor
present
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8228736A
Other languages
Japanese (ja)
Inventor
Yoichi Tsunoda
洋一 角田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP8228736A priority Critical patent/JPH1074778A/en
Publication of JPH1074778A publication Critical patent/JPH1074778A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/83141—Guiding structures both on and outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is free from package cracking even when the device is subjected to cycling tests and solder reflow tests and is improved in moisture resistance. SOLUTION: A semiconductor chip l and an island 2 are mechanically fixed to each other by providing a plurality of projecting sections 3 at regular intervals on the rear surface of the chip and recessed section 7 on the surface of the island 2 so as to surround the projecting sections 3, and then, inserting the projecting sections 3 into their corresponding recessed sections 7. Since no die bonding agent is used, the occurrence of package cracking caused by the expansion of the moisture, etc., contained in a die bonding agent can be prevented during the course of a heat treatment process.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は半導体装置に関し、
特に半導体チップをプラスチックなどの樹脂により封止
する樹脂封止型の半導体装置に関する。The present invention relates to a semiconductor device,
In particular, the present invention relates to a resin-sealed semiconductor device in which a semiconductor chip is sealed with a resin such as plastic.

【０００２】[0002]

【従来の技術】従来の半導体装置は、図４（ａ）及び図
４（ｂ）に示すように半導体チップ１をアイランド２に
銀ペーストなどのダイボンド材９を用いて固着し、ボン
ディングワイヤーで半導体チップ１上に固定して配置し
ているボンディングパッド１１とインナーリード１０と
を結線し、樹脂封止を行った後、アウターリード６を加
工成形する方法が採られている。2. Description of the Related Art In a conventional semiconductor device, as shown in FIGS. 4 (a) and 4 (b), a semiconductor chip 1 is fixed to an island 2 using a die bond material 9 such as a silver paste, and the semiconductor chip is bonded with a bonding wire. A method is employed in which the bonding pads 11 fixedly arranged on the chip 1 are connected to the inner leads 10, and after sealing with resin, the outer leads 6 are processed and formed.

【０００３】[0003]

【発明が解決しようとする課題】従来の半導体装置で
は、アイランド２と半導体チップ１の熱膨張係数が大き
く異なるため、ダイボンド材９が剥離し易いという問題
がある。In the conventional semiconductor device, there is a problem that the die bonding material 9 is easily peeled off because the island 2 and the semiconductor chip 1 have greatly different coefficients of thermal expansion.

【０００４】また、ダイボンド材９の吸水率が高いた
め、加熱時にダイボンド材９に含まれる水分が気化する
ため、温度サイクル試験や半田リフロー試験などの信頼
性試験において、ダイボンド材が起点となり、パッケー
ジクラックが発生するという問題がある。Further, since the water absorption of the die bond material 9 is high, the moisture contained in the die bond material 9 evaporates at the time of heating. There is a problem that cracks occur.

【０００５】最近、半導体チップ１には、動作周波数が
１００ＭＨｚを越えるような高速動作をする回路が搭載
されており、このため半導体チップ１の消費電力は、ゆ
うに数ワットを越えるようになってきている。したがっ
て、半導体チップ１で発生する熱をパッケージ外部に効
率よく放熱するため、アイランド２の材質としては熱伝
導率に優れている銅を主成分とする金属材料が使われる
ようになっている。Recently, the semiconductor chip 1 is equipped with a circuit that operates at a high speed such that the operating frequency exceeds 100 MHz. Therefore, the power consumption of the semiconductor chip 1 has just exceeded several watts. ing. Therefore, in order to efficiently radiate the heat generated in the semiconductor chip 1 to the outside of the package, a metal material mainly composed of copper, which has excellent thermal conductivity, is used as the material of the island 2.

【０００６】しかしながら、銅を主成分とする金属材料
は、熱伝導率的には優れているものの、半導体チップ１
の材質であるシリコンとは熱膨張係数が大きく異なり、
ダイボンド材９が剥離し易いという問題は深刻である。[0006] However, although the metal material containing copper as a main component is excellent in thermal conductivity, the semiconductor chip 1 has a high thermal conductivity.
The thermal expansion coefficient is significantly different from that of silicon,
The problem that the die bond material 9 is easily peeled is serious.

【０００７】さらに、半導体チップ１に搭載される回路
素子は最近急速に大規模化が進み、半導体チップ１のチ
ップサイズは増大の一途をたどっている。このため、半
導体チップ１とアイランド２との境界に位置するダイボ
ンド材９に、半導体チップ１とアイランド２の熱膨張係
数の差による歪みが一層集中し、ダイボンド材９が剥離
するという問題がクローズアップされてきている。Further, circuit elements mounted on the semiconductor chip 1 have recently been rapidly increasing in scale, and the chip size of the semiconductor chip 1 is steadily increasing. For this reason, the strain due to the difference in the thermal expansion coefficient between the semiconductor chip 1 and the island 2 is further concentrated on the die bonding material 9 located at the boundary between the semiconductor chip 1 and the island 2, and the problem that the die bonding material 9 is peeled off is a close-up. Have been.

【０００８】このため、本発明の目的は温度サイクル試
験や半田リフロー試験などの信頼性試験において発生す
るダイボンド材の剥離や、ダイボンド材を起点としたパ
ッケージクラックの発生を防止し信頼性を向上した半導
体装置を提供することにある。Therefore, an object of the present invention is to improve the reliability by preventing peeling of the die bond material and occurrence of a package crack originating from the die bond material which occur in a reliability test such as a temperature cycle test or a solder reflow test. It is to provide a semiconductor device.

【０００９】また、本発明の他の目的はダイボンド材を
使用せずに製造コストを削減した半導体装置を提供する
ことにある。Another object of the present invention is to provide a semiconductor device in which the manufacturing cost is reduced without using a die bonding material.

【００１０】[0010]

【課題を解決するための手段】そのため、本発明による
半導体装置は、半導体チップ搭載部に半導体チップを搭
載固定し、複数のリードと前記半導体チップの各電極と
を複数のボンディングワイヤーにより接続し、前記半導
体チップ搭載部と前記半導体チップと前記リードの所定
の部分と前記ボンディングワイヤーとを封止樹脂により
封止した半導体装置において、前記半導体チップの裏面
に形成した複数の凸部を、これらの凸部を取り囲むよう
に前記半導体チップ搭載部に形成した凹部にそれぞれ挿
入することにより、前記半導体チップと前記半導体チッ
プ搭載部とを固定したことを特徴としている。Therefore, in a semiconductor device according to the present invention, a semiconductor chip is mounted and fixed on a semiconductor chip mounting portion, and a plurality of leads and respective electrodes of the semiconductor chip are connected by a plurality of bonding wires. In a semiconductor device in which the semiconductor chip mounting portion, the semiconductor chip, predetermined portions of the leads, and the bonding wires are sealed with a sealing resin, a plurality of protrusions formed on the back surface of the semiconductor chip are formed by using these protrusions. The semiconductor chip and the semiconductor chip mounting portion are fixed by being inserted into recesses formed in the semiconductor chip mounting portion so as to surround the portion.

【００１１】[0011]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.

【００１２】図１（ａ）は本発明の半導体装置の第１の
実施の形態を示す構造断面図、図１（ｂ）は本発明の半
導体装置の第１の実施の形態を示す透視的平面図、図１
（ｃ）は本発明の半導体装置の製造工程の一部を説明す
るための説明図である。なお、従来例と対応する部分に
は同一符号を付している。FIG. 1A is a structural sectional view showing a first embodiment of the semiconductor device of the present invention, and FIG. 1B is a perspective plan view showing the first embodiment of the semiconductor device of the present invention. Figure, Figure 1
FIG. 3C is an explanatory diagram for describing a part of the manufacturing process of the semiconductor device of the present invention. Parts corresponding to those of the conventional example are denoted by the same reference numerals.

【００１３】本発明の半導体装置は、図１（ｃ）に示す
ように半導体チップ１の裏面をドライエッチングなどの
方法により、部分的にアイランド２の厚さ約１５０μよ
りも薄い５０〜１５０μの高さで、凸部３を半導体チッ
プ１の裏面全体に渡って等間隔に形成する。この凸部３
の形状としては、図１（ｂ）に示す丸形のほかに四角形
や正多角形又は他の任意の形状でもよい。In the semiconductor device of the present invention, as shown in FIG. 1C, the back surface of the semiconductor chip 1 is partially etched by a method such as dry etching to a height of 50 to 150 .mu. Now, the convex portions 3 are formed at equal intervals over the entire back surface of the semiconductor chip 1. This convex part 3
May be a square, a regular polygon, or any other shape in addition to the round shape shown in FIG. 1 (b).

【００１４】凸部３どうしの間隔は、半導体チップ１の
歪みを緩和するためには小さい方が好ましいが、あまり
小さくすると半導体チップ１の材質であるシリコンの機
械的強度が保てなくなるので、半導体チップ１の面積や
厚さ及びパッケージの種類などを考慮して決定する。It is preferable that the interval between the projections 3 is small in order to alleviate the distortion of the semiconductor chip 1. However, if the interval is too small, the mechanical strength of silicon, which is the material of the semiconductor chip 1, cannot be maintained. It is determined in consideration of the area and thickness of the chip 1 and the type of the package.

【００１５】次に、半導体チップ１の裏面に形成した凸
部３よりも少し大きい凹部７をエッチング加工やプレス
加工などによりアイランド２に設け、図１（ｃ）に示す
ように半導体チップ１の裏面に設けた凸部３をアイラン
ド２に設けた凹部７に挿入して、半導体チップ１とアイ
ランド２を機械的に固定する。Next, a concave portion 7 slightly larger than the convex portion 3 formed on the back surface of the semiconductor chip 1 is provided on the island 2 by etching or pressing, and as shown in FIG. The semiconductor chip 1 and the island 2 are mechanically fixed by inserting the convex portion 3 provided on the island 2 into the concave portion 7 provided on the island 2.

【００１６】このあと、封止樹脂５によって半導体チッ
プ１及びアイランド２を封止し、アウターリード６を整
形して図１（ａ）に示す本発明の半導体装置を作成す
る。Thereafter, the semiconductor chip 1 and the island 2 are sealed with the sealing resin 5, and the outer leads 6 are shaped to form the semiconductor device of the present invention shown in FIG.

【００１７】本実施の形態において、半導体チップ１と
アイランド２との熱膨張係数の違いにより、半導体チッ
プ１の裏面に平行な方向に沿って大きな歪みが発生して
も、従来の半導体装置のように半導体チップ１とアイラ
ンド２はダイボンド材９により強く固着されておらず、
半導体チップ１の裏面に形成した凸部３とアイランド２
の表面に形成した凹部７との間隙が歪みを緩和する効果
がある。In the present embodiment, even if a large distortion occurs in a direction parallel to the back surface of the semiconductor chip 1 due to a difference in the thermal expansion coefficient between the semiconductor chip 1 and the island 2, the conventional semiconductor device will not be described. In addition, the semiconductor chip 1 and the island 2 are not firmly fixed by the die bonding material 9,
Convex portion 3 and island 2 formed on the back surface of semiconductor chip 1
The gap with the concave portion 7 formed on the surface has the effect of alleviating distortion.

【００１８】また、本発明の半導体装置は、銀ペースト
などのダイボンド材９を用いないので、ダイボンド材９
が剥離したり、加熱時にダイボンド材９に含まれる水分
が気化し、温度サイクル試験や半田リフロー試験などの
信頼性試験において、ダイボンド材が起点となり、パッ
ケージクラックが発生するという問題は発生せず、極め
て信頼性が高い。Further, since the semiconductor device of the present invention does not use the die bonding material 9 such as a silver paste, the die bonding material 9 is not used.
Does not peel off, or the moisture contained in the die bond material 9 evaporates at the time of heating. In a reliability test such as a temperature cycle test or a solder reflow test, the die bond material becomes a starting point and a problem that a package crack occurs does not occur. Extremely reliable.

【００１９】次に、図２（ａ）及び図２（ｂ）を参照し
て、本発明の第２の実施の形態による半導体装置につい
て説明する。Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS. 2 (a) and 2 (b).

【００２０】図２（ａ）は本発明の半導体装置の第２の
実施の形態を示す構造断面図、図２（ｂ）は本発明の半
導体装置の第２の実施の形態を示す透視的平面図であ
る。FIG. 2A is a structural sectional view showing a second embodiment of the semiconductor device of the present invention, and FIG. 2B is a perspective plan view showing the second embodiment of the semiconductor device of the present invention. FIG.

【００２１】本実施の形態においては、半導体チップ１
の裏面全体に渡って図２（ｂ）に示すように、複数の平
面上の階段状パターンからなる凹部１２を形成し、この
凹部１２に対しアイランド２の表面に形成した凸部１３
を挿入し、半導体チップ１とアイランド２を固定する。In this embodiment, the semiconductor chip 1
As shown in FIG. 2B, a concave portion 12 composed of a plurality of planar step-like patterns is formed over the entire rear surface of the island 2, and the convex portion 13 formed on the surface of the island 2 is formed on the concave portion 12.
And the semiconductor chip 1 and the island 2 are fixed.

【００２２】本実施の形態による半導体装置において
も、第１の実施の形態と同様に、半導体チップ１とアイ
ランド２はダイボンド材９により強く固着されておら
ず、半導体チップ１の裏面に形成した凹部１２とアイラ
ンド２の表面に形成した凸部１３とにより半導体チップ
１とアイランド２が機械的に固定されているので、半導
体チップ１に生じる半導体チップ１とアイランド２の熱
膨張係数との違いによる歪みを低減することができる。Also in the semiconductor device according to the present embodiment, similarly to the first embodiment, the semiconductor chip 1 and the island 2 are not firmly fixed by the die bonding material 9, but are formed on the back surface of the semiconductor chip 1. Since the semiconductor chip 1 and the island 2 are mechanically fixed to each other by the protrusions 12 formed on the surface of the island 2, distortion caused by a difference between the thermal expansion coefficients of the semiconductor chip 1 and the island 2 caused in the semiconductor chip 1. Can be reduced.

【００２３】次に、図３（ａ）及び図３（ｂ）を参照し
て、本発明の第３の実施の形態による半導体装置につい
て説明する。Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 3 (a) and 3 (b).

【００２４】図３（ａ）は本発明の半導体装置の第３の
実施の形態を示す構造断面図、図３（ｂ）は本発明の半
導体装置の第３の実施の形態を示す透視的平面図であ
る。FIG. 3A is a structural sectional view showing a third embodiment of the semiconductor device of the present invention, and FIG. 3B is a perspective plan view showing the third embodiment of the semiconductor device of the present invention. FIG.

【００２５】本実施の形態においては、アイランド２に
貫通口８をアイランド２の全面に渡って均等にエッチン
グ加工やプレス加工などにより形成し、この貫通口８に
半導体チップ１の裏面に設けた凸部３を挿入し、半導体
チップ１とアイランド２を固定する。In the present embodiment, a through hole 8 is formed in the island 2 uniformly over the entire surface of the island 2 by etching or pressing, and the through hole 8 is provided on the back surface of the semiconductor chip 1. The part 3 is inserted, and the semiconductor chip 1 and the island 2 are fixed.

【００２６】通常、アイランド２の厚さ約１５０μに対
し半導体チップ１の厚さは３５０〜４００μと厚いが、
アイランド２に配置した凹部をアイランド２の厚さ方向
に貫通させて貫通口８を設け、この貫通口８に対して半
導体チップ１の裏面に形成した凸部３を挿入する方法を
採ることにより、半導体チップ１の裏面に形成する凸部
３の高さに対する制限は大幅に緩和される。Normally, the thickness of the semiconductor chip 1 is as thick as 350 to 400 μ with respect to the thickness of the island 2 of about 150 μ.
By adopting a method of penetrating the concave portion arranged on the island 2 in the thickness direction of the island 2 to form a through hole 8 and inserting the convex portion 3 formed on the back surface of the semiconductor chip 1 into the through hole 8, The restriction on the height of the protrusion 3 formed on the back surface of the semiconductor chip 1 is greatly eased.

【００２７】さらに、半導体チップ１の裏面に形成する
凸部３の高さを大きくとることができるため、半導体チ
ップ１とアイランド２との機械的な固定を強くすること
ができ、半導体チップ１がアイランド２から浮いてしま
うことがないという利点がある。Further, since the height of the projection 3 formed on the back surface of the semiconductor chip 1 can be increased, the mechanical fixation between the semiconductor chip 1 and the island 2 can be strengthened, and the semiconductor chip 1 There is an advantage that it does not float off the island 2.

【００２８】[0028]

【発明の効果】以上説明したように、本発明による半導
体装置は、半導体チップとアイランドとの熱膨張係数の
違いにより半導体チップの裏面に平行な方向に沿って大
きな歪みが発生しても、半導体チップとアイランドはダ
イボンド材より強く固着されておらず、半導体チップの
裏面に形成した凸部とアイランドの表面に形成した凹部
とは機械的に固定されているのみであることから、半導
体チップが歪みにより破壊するという問題は生じない。As described above, in the semiconductor device according to the present invention, even if a large strain is generated along the direction parallel to the back surface of the semiconductor chip due to the difference in the thermal expansion coefficient between the semiconductor chip and the island, Since the chip and the island are not firmly bonded to each other than the die bonding material, and only the convex portion formed on the back surface of the semiconductor chip and the concave portion formed on the surface of the island are mechanically fixed, the semiconductor chip is distorted. The problem of destruction does not arise.

【００２９】さらに半導体チップの裏面に形成した凸部
とアイランドの表面に形成した凹部の間隙が歪みを緩和
する効果がある。Further, the gap between the convex portion formed on the back surface of the semiconductor chip and the concave portion formed on the surface of the island has an effect of alleviating distortion.

【００３０】また、本発明の半導体装置は、銀ペースト
などのダイボンド材を用いないので、ダイボンド材が剥
離したり、加熱時にダイボンド材に含まれる水分が気化
し、温度サイクル試験や半田リフロー試験などの信頼性
試験において、ダイボンド材が起点となり、パッケージ
クラックが発生するという問題は発生しない。このた
め、パッケージクラックから水分が進入し耐湿性が劣化
することもなく極めて信頼性が高い。Further, since the semiconductor device of the present invention does not use a die bonding material such as a silver paste, the die bonding material is peeled off, or moisture contained in the die bonding material is vaporized at the time of heating, so that a temperature cycle test, a solder reflow test, etc. In the reliability test described above, the problem that a package crack occurs due to a die bond material as a starting point does not occur. For this reason, the reliability is extremely high without moisture entering from package cracks and deteriorating moisture resistance.

【００３１】また、本発明の半導体装置はダイボンド材
を使用しないので、半導体装置の製造コストを低減する
ことができる。Since the semiconductor device of the present invention does not use a die bonding material, the manufacturing cost of the semiconductor device can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の半導体装置の第１の実施の形態を示す
図面であり、図１（ａ）は構造断面図、図１（ｂ）は透
視的平面図、図１（ｃ）製造工程の一部を説明するため
の説明図である。FIGS. 1A and 1B are drawings showing a first embodiment of a semiconductor device according to the present invention, wherein FIG. 1A is a structural sectional view, FIG. 1B is a perspective plan view, and FIG. FIG. 4 is an explanatory diagram for describing a part of the above.

【図２】本発明の半導体装置の第２の実施の形態を示す
図面であり、図２（ａ）は構造断面図、図２（ｂ）は透
視的平面図である。FIGS. 2A and 2B are drawings showing a second embodiment of the semiconductor device of the present invention, wherein FIG. 2A is a structural sectional view and FIG. 2B is a perspective plan view.

【図３】本発明の半導体装置の第３の実施の形態を示す
図面であり、図３（ａ）は構造断面図、図３（ｂ）は透
視的平面図である。3A and 3B are drawings showing a third embodiment of the semiconductor device of the present invention, wherein FIG. 3A is a structural cross-sectional view and FIG. 3B is a perspective plan view.

【図４】従来の半導体装置を示す図面であり、図４
（ａ）は構造断面図、図４（ｂ）は透視的平面図であ
る。FIG. 4 is a drawing showing a conventional semiconductor device, and FIG.
4A is a structural sectional view, and FIG. 4B is a perspective plan view.

【符号の説明】[Explanation of symbols]

１ 半導体チップ ２ アイランド ３ 半導体チップ１の裏面凸部 ４ ボンディングワイヤー ５ 封止樹脂 ６ アウターリード ７ アイランド２に形成した凹部 ８ アイランド２の貫通口 ９ ダイボンド材 １０ インナーリード １１ ボンディングパッド １２ 半導体チップ１の裏面に形成した階段状パター
ンからなる凹部 １３ アイランド２の表面に形成した凸部REFERENCE SIGNS LIST 1 semiconductor chip 2 island 3 back surface convex portion of semiconductor chip 1 4 bonding wire 5 sealing resin 6 outer lead 7 concave portion formed in island 2 8 through hole of island 2 9 die bonding material 10 inner lead 11 bonding pad 12 of semiconductor chip 1 A concave portion composed of a step-like pattern formed on the back surface 13 A convex portion formed on the surface of the island 2

Claims (3)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップ搭載部に半導体チップを搭
載固定し、複数のリードと前記半導体チップの各電極と
を複数のボンディングワイヤーにより接続し、前記半導
体チップ搭載部と前記半導体チップと前記リードの所定
の部分と前記ボンディングワイヤーとを封止樹脂により
封止した半導体装置において、 前記半導体チップの裏面に形成した複数の凸部を、これ
らの凸部を取り囲むように前記半導体チップ搭載部に形
成した凹部にそれぞれ挿入することにより、前記半導体
チップと前記半導体チップ搭載部とを固定したことを特
徴とする半導体装置。A semiconductor chip is mounted and fixed on a semiconductor chip mounting portion, a plurality of leads are connected to respective electrodes of the semiconductor chip by a plurality of bonding wires, and the semiconductor chip mounting portion, the semiconductor chip, and the leads are connected to each other. In a semiconductor device in which a predetermined portion and the bonding wire are sealed with a sealing resin, a plurality of convex portions formed on a back surface of the semiconductor chip are formed on the semiconductor chip mounting portion so as to surround these convex portions. A semiconductor device, wherein the semiconductor chip and the semiconductor chip mounting portion are fixed by being inserted into recesses, respectively. 【請求項２】 前記半導体チップ搭載部に形成した前記
凹部は、前記半導体チップ搭載部の表面から裏面にかけ
て穿たれていることを特徴とする請求項１記載の半導体
装置。2. The semiconductor device according to claim 1, wherein the concave portion formed in the semiconductor chip mounting portion is formed from a front surface to a rear surface of the semiconductor chip mounting portion. 【請求項３】 前記半導体チップ搭載部に形成した前記
凹部の形状は、対応する前記半導体チップの裏面に形成
した前記凸部の形状と相似的に同一であることを特徴と
する請求項１又は２記載の半導体装置。3. The semiconductor device according to claim 1, wherein the shape of the concave portion formed on the semiconductor chip mounting portion is similar to the shape of the convex portion formed on the back surface of the corresponding semiconductor chip. 3. The semiconductor device according to 2.
JP8228736A 1996-08-29 1996-08-29 Semiconductor device Pending JPH1074778A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8228736A JPH1074778A (en) 1996-08-29 1996-08-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8228736A JPH1074778A (en) 1996-08-29 1996-08-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH1074778A true JPH1074778A (en) 1998-03-17

Family

ID=16881021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8228736A Pending JPH1074778A (en) 1996-08-29 1996-08-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH1074778A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10125905C1 (en) * 2001-05-28 2002-11-28 Infineon Technologies Ag Releasable coupling between IC chip and carrier uses interlocking mechanical coupling elements provided by IC chip and carrier
KR100691942B1 (en) * 2001-01-15 2007-03-08 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100691942B1 (en) * 2001-01-15 2007-03-08 앰코 테크놀로지 코리아 주식회사 Semiconductor package and method for manufacturing the same
DE10125905C1 (en) * 2001-05-28 2002-11-28 Infineon Technologies Ag Releasable coupling between IC chip and carrier uses interlocking mechanical coupling elements provided by IC chip and carrier
SG104966A1 (en) * 2001-05-28 2004-07-30 Infineon Technologies Ag Self-adhering chip

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