JPS61160965A - Semiconductor ic device - Google Patents
Semiconductor ic deviceInfo
- Publication number
- JPS61160965A JPS61160965A JP106785A JP106785A JPS61160965A JP S61160965 A JPS61160965 A JP S61160965A JP 106785 A JP106785 A JP 106785A JP 106785 A JP106785 A JP 106785A JP S61160965 A JPS61160965 A JP S61160965A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- transistor
- base
- emitter
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 abstract description 15
- 230000003071 parasitic effect Effects 0.000 abstract description 6
- 239000011229 interlayer Substances 0.000 abstract description 4
- 230000007423 decrease Effects 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 2
- 239000012535 impurity Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は高性能のＭＯＳ トランジスタと高速のバブポ
ーラトランジスタを一体化した半導体集積回路装置の構
造に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a semiconductor integrated circuit device that integrates a high-performance MOS transistor and a high-speed bubble polar transistor.
従来の技術
従来のバイポーラトランジスタ、ＭＯＳトランジスタを
一体化した半導体集積回路装置を第１０図に示す。2. Description of the Related Art A conventional semiconductor integrated circuit device in which a bipolar transistor and a MOS transistor are integrated is shown in FIG.
図において、１はＰ形基板、２はバイポーラトランジス
タのｎ 埋込部、３はＭＯＳトランジスの
ｊ１＋埋込部、４はｎ−ウェルでバイポーラトランジス
タのコレクタ、５はｎ−ウェル、６は分離酸化膜、７は
バイポーラトランジスタのｐ形ベース、８はバイポーラ
トランジスタのｐ 形ベースコンタクト層、９はｐ 領
域でＭＯＳトランジスタのソース、１０はｐ 領域でＭ
ＯＳトランジスタのドレイン、１１はｎ 領域でペース
コンイクト層、１２はｎ 領域でエミッタ、１３はコレ
クタ、１４はエミッタ、１６はベース、１６はソース電
極、１７はドレイン電極、１８はゲート酸化膜、１９は
ゲート電極である。このような構造において、ＭＯＳト
ランジスタは、ゲート電極１８とソース電極１６（又は
ドレイン電極１７）は２゛層構造になっているので、電
極間の距離を小さくすることができる。そのためトラン
ジスタのサイズが小さくなり、寄生容量が下がる。これ
はトランジスタの性能を上げることになる。一方バイボ
ーラトランジスタはベース電極８とエミッタ電極１２は
一層構造になっているため、電極間の距離を広くとる必
要がある。このためベース面積が大きくなり、寄生容量
が上がる。これはトランジスタのスピードを著しく低減
させることになる。In the figure, 1 is the P-type substrate, 2 is the n-buried part of the bipolar transistor, 3 is the j1+ buried part of the MOS transistor, 4 is the n-well and the collector of the bipolar transistor, 5 is the n-well, and 6 is the isolated oxide. 7 is the p-type base of the bipolar transistor, 8 is the p-type base contact layer of the bipolar transistor, 9 is the p-region and the source of the MOS transistor, 10 is the p-region and M
The drain of the OS transistor, 11 is an n-region and a spaceconducting layer, 12 is an emitter in an n-region, 13 is a collector, 14 is an emitter, 16 is a base, 16 is a source electrode, 17 is a drain electrode, 18 is a gate oxide film, 19 is a gate electrode. In such a structure, since the gate electrode 18 and the source electrode 16 (or drain electrode 17) have a two-layer structure in the MOS transistor, the distance between the electrodes can be reduced. This reduces the size of the transistor and reduces parasitic capacitance. This will improve the performance of the transistor. On the other hand, since the base electrode 8 and emitter electrode 12 of the bibolar transistor have a single layer structure, it is necessary to provide a wide distance between the electrodes. This increases the base area and increases parasitic capacitance. This will significantly reduce the speed of the transistor.
従ってこのような従来の構造では、高性能のＭＯＳトラ
ンジスタと高速のバイポーラトランジスタを両者の特性
を互に損なうことなしに一体化することは難しいもので
あった。Therefore, with such a conventional structure, it is difficult to integrate a high-performance MOS transistor and a high-speed bipolar transistor without mutually damaging the characteristics of both.
発明が解決しようとする問題点
このような従来の半導体集積回路装置ではｌＭＯＳトラ
ンジスタの特性は良いが、同一基板に形成されたバイポ
ーラトランジスタの高速化は十分でない。特にバイポー
ラトランジスタのベース電極とエミッタ電極との距離を
長くとる必要があるためベース領域が大きくなり、その
ためベース容量の増大により高速化が損なわれる。本発
明はかかる点に鑑みてなされたもので、簡単な構成で高
性能のＭＯＳ トランジスタと高速なバイポーラトラン
ジスタを互いの性能を損うことなく良好に一体化するこ
とができる半導体集積回路装置を提供することを目的と
している。Problems to be Solved by the Invention Although the characteristics of the IMOS transistor in such a conventional semiconductor integrated circuit device are good, the speed of the bipolar transistor formed on the same substrate is not sufficiently high. In particular, it is necessary to increase the distance between the base electrode and emitter electrode of a bipolar transistor, which increases the base region, which impairs high speed performance due to an increase in base capacitance. The present invention has been made in view of the above, and provides a semiconductor integrated circuit device that can satisfactorily integrate a high-performance MOS transistor and a high-speed bipolar transistor with a simple configuration without impairing each other's performance. It is intended to.
問題点を解決するだめの手段
本発明は上記問題点を解決するため、同一の工程で形成
したＭＯＳトランジスタのゲート電極とバイポーラトラ
ンジスタのエミッタ電極を有し。Means for Solving the Problems In order to solve the above problems, the present invention has a gate electrode of a MOS transistor and an emitter electrode of a bipolar transistor formed in the same process.
かつ、上記ゲート電極とエミッタ電極を被覆する絶縁膜
にそれぞれ開口を設けて形成されたソース。and a source formed by providing an opening in an insulating film covering the gate electrode and the emitter electrode.
ドレイン電極及びベース電極を備えたものである。It is equipped with a drain electrode and a base electrode.
エミッタ電極とベース電極は２層構造になっておりゲー
ト電極とソース電極（ドレイン電極）は２層構造になっ
ている。The emitter electrode and base electrode have a two-layer structure, and the gate electrode and source electrode (drain electrode) have a two-layer structure.
作用
本発明は上記の構造によシ、バイポーラトランジスタの
エミッタ電極とベース電極間の距離を短縮し、ベース、
コレクタ間の容量を小さくして。Effect of the present invention In accordance with the above structure, the distance between the emitter electrode and the base electrode of a bipolar transistor is shortened, and the distance between the base and base electrodes is reduced.
Reduce the capacitance between collectors.
ＭＯＳトランジスタの高性能を保ちながら、バイポーラ
トランジスタの高速化を実現する。Achieving high speed bipolar transistors while maintaining the high performance of MOS transistors.
実施例
第１図は本発明の一実施例における半導体集積回路装置
の断面図である。図において、２０はｐ形基板、２１は
ＭＯＳトランジスタの計理込部。Embodiment FIG. 1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention. In the figure, 20 is a p-type substrate, and 21 is a calculation section of a MOS transistor.
２２はバイポーラトランジスタのｎ十埋込部、２３はｎ
−ウェル、２４はｎ−ウェルでバイポーラトランジスタ
のコレクタ、２５は分離酸化膜、２６ハｐ十領域でＭＯ
Ｓトランジスタのソース、２７はｐ十領域でＭＯＳトラ
ンジスタのドレイン。22 is the n-buried portion of the bipolar transistor, and 23 is the n-buried portion of the bipolar transistor.
- well, 24 is an n-well and is the collector of a bipolar transistor, 25 is an isolation oxide film, and 26 is a hap region for MO
The source of the S transistor, 27 is the p region and the drain of the MOS transistor.
２８はバイポーラトランジスタのｐ十形ベースコンタク
ト、２９はｐ領域でＭＯＳトランジスタのソース、３０
はｐ領域でＭＯＳトランジスタのドレイン、３１はｐ領
域でバイポーラトランジスタの外部ベース、３２はｐ領
域でバイポーラトランジスタの内部ベース、３３はｎ十
領域でバイポーラトランジスタのエミッタ、３４はｎ十
領域でバイポーラトランジスタのコレクタコンタクト、
３５はゲート酸化膜、３６はゲート電極、３りはエミッ
タ電極、３８は多層用の眉間絶縁膜、３９はソース電極
、４０はビレ１イン電極、４１はベース電極、４２はコ
レクタ電極、４３はサイドウオールである。28 is the p-type base contact of the bipolar transistor, 29 is the p region and the source of the MOS transistor, 30
is the drain of the MOS transistor in the p region, 31 is the external base of the bipolar transistor in the p region, 32 is the internal base of the bipolar transistor in the p region, 33 is the emitter of the bipolar transistor in the n0 region, and 34 is the bipolar transistor in the n0 region. collector contact,
35 is a gate oxide film, 36 is a gate electrode, 3 is an emitter electrode, 38 is a glabella insulating film for multilayer, 39 is a source electrode, 40 is a fin 1-in electrode, 41 is a base electrode, 42 is a collector electrode, 43 is a It's a side wall.
第１図に示した構造において、ＭＯＳ トランジスタは
ゲート電極３６とソース電極３９（又はドレイン電極４
０）が層間絶縁膜３８を介して２層ｗｔ造になっている
ので電極間の距離を小さくすることができる。そのため
トランジスタのサイズが小さくなり、寄生容量が下がシ
、トランジスタの性能が上がる。バイポーラトランジス
タにおいてもエミッタ電極３７とベース電極４１が層間
絶縁膜３８を介して２層構造になっているので電極間の
距離を小さくすることができる。そのためトランジスタ
のベース面積が小さくなシ、寄生容量が下がり、トラン
ジスタのスピードが上がる。ベース電極４１とソース電
極３９（又はドレイン電極４０）は同一の工程で形成さ
れ、ゲート電極３６とエミッタ電極３７は同一の工程で
形成される。In the structure shown in FIG. 1, the MOS transistor has a gate electrode 36 and a source electrode 39 (or drain electrode 4).
0) has a two-layer wt structure with an interlayer insulating film 38 in between, so the distance between the electrodes can be reduced. This reduces the size of the transistor, reduces parasitic capacitance, and improves transistor performance. In the bipolar transistor as well, since the emitter electrode 37 and the base electrode 41 have a two-layer structure with the interlayer insulating film 38 in between, the distance between the electrodes can be reduced. This reduces the base area of the transistor, reduces parasitic capacitance, and increases the speed of the transistor. The base electrode 41 and the source electrode 39 (or the drain electrode 40) are formed in the same process, and the gate electrode 36 and the emitter electrode 37 are formed in the same process.
ゲート電極３６とエミッタ電極３７の材料としては、多
結晶Ｓｉ、シリサイド、高融点金属等が使用される。As the material for the gate electrode 36 and the emitter electrode 37, polycrystalline Si, silicide, high melting point metal, etc. are used.
次に第２図〜第９図をもとに、上記半導体集積回路装置
の構造を実現するだめの製造プロセスを説明する。Next, a manufacturing process for realizing the structure of the semiconductor integrated circuit device will be explained based on FIGS. 2 to 9.
第２図において、ｎ−ウェル領域２３．２４を分離する
酸化膜２５が形成されている。ｎ−ウェル領域２３には
ゲート酸化膜３５．ｐ形の不純物領域ａ２．ｎ％の不純
物領域３３が形成されている。In FIG. 2, an oxide layer 25 is formed which separates the n-well regions 23,24. A gate oxide film 35 is formed in the n-well region 23. p-type impurity region a2. An n% impurity region 33 is formed.
次に第３図において全面に、多結晶Ｓｉ又はシリサイド
又は高融点金属を堆積したのち、フォトエツチング工程
によりゲート電極３６．エミッタ電極３７を形成する。Next, as shown in FIG. 3, after polycrystalline Si, silicide, or high melting point metal is deposited on the entire surface, the gate electrode 36. An emitter electrode 37 is formed.
次に第４図において、エミッタ電極３７をマスクとして
、ｐ形の不純物領域３２．ｎ＋形の不純物領域３３をエ
ツチングすることによりｐ形の活性ベース領域３２．ｎ
十形のエミッタ領域３３を形成する・
次に第６図において、ｐ形め不純物を全面にインブラン
ティング（注入）して、低濃度のソース領域２９．ドレ
イン領域３０．低濃度の外部ベース３１を同時に形成す
る。この時、ゲート電極３６の直下及びエミッタ電極３
７の直下には不純物が入らないようにインブランティン
グのエネルギーを設定する。Next, in FIG. 4, using the emitter electrode 37 as a mask, p-type impurity regions 32. By etching the n+ type impurity region 33, a p type active base region 32. n
Forming a ten-shaped emitter region 33 Next, as shown in FIG. 6, p-type impurities are implanted over the entire surface to form a low concentration source region 29. Drain region 30. A low concentration external base 31 is formed at the same time. At this time, directly under the gate electrode 36 and the emitter electrode 3
Implanting energy is set so that impurities do not enter directly under 7.
次に第６図において、全面にＣｖＤのＳｉＯ□層を形成
する。Next, in FIG. 6, a CvD SiO□ layer is formed on the entire surface.
次に第７図において、異方性のドライエツチングを用い
て、ＧＶＤｓｉｏ□２３をエツチングしてゲート電極３
６．エミッタ電極３７の側面のみに残しサイドウオール
４３を形成する。ソース、ドレイン領域２９．３０及び
外部ベース３１上のＣＶＤ５ｉＯ□層４３はエツチング
される。Next, in FIG. 7, the gate electrode 3 is etched using anisotropic dry etching.
6. A side wall 43 is formed leaving only the side surface of the emitter electrode 37. The CVD5iO□ layer 43 over the source and drain regions 29, 30 and extrinsic base 31 is etched.
次に第８図において、全面にｐ形の不純物をイオン注入
して、ｐ＋のソース２６．ドレイン２７゜ｐ＋の外部ベ
ース２８を同時に形成する。Next, in FIG. 8, p-type impurity ions are implanted into the entire surface of the p+ source 26. The external base 28 of the drain 27°p+ is formed at the same time.
ゲート電極３６．サイドウオール４３．エミッタ電極３
７の直下にはインブランティングの不純物が入らないよ
うにエネルギーを設定する。ドレイン領域３０は低濃度
のドレイン領域でいわゆるＬ Ｄ Ｄ （ｌｉｇｈ、ｔ
ｌｙ ｄｏｐａｄ ｄｒａｉｎ）構造となッテオリ、ホ
ットエレクトロンの低減に効果がある。また低濃度の外
部ベース２８はエミッタ、ベース間の耐圧向上に効果が
ある。Gate electrode 36. Side wall 43. Emitter electrode 3
The energy is set so that impurities from im-blanting do not enter directly under 7. The drain region 30 is a low concentration drain region and has a so-called L D D (light, t
This structure is effective in reducing hot electrons. Furthermore, the low concentration external base 28 is effective in improving the breakdown voltage between the emitter and the base.
次に第９図において、全面にＯＶ Ｄ Ｓｉ０□３８を
堆積する。次にソースコンタクト４４．ドレインコンタ
クト４５．ベースコンタクト４６．４７を開孔する。Next, in FIG. 9, OV D Si0□ 38 is deposited on the entire surface. Next, source contact 44. Drain contact 45. Base contacts 46, 47 are drilled.
最後に第１図に示すように、ソース電極３９゜ドレイン
電極４０．ベース電極４１．コレクタ電極４２を同時に
形成する。第２図〜第９図の工程ではバイポーラトラン
ジスタのｎ 埋込部２２゜ＭＯＳトランジスタのｎ十埋
込部２１．ｐ形基板２０、ｎ十領域でバイポーラトラン
ジスタのコレクタコンタクト３４の形成手順を示してい
ないが。Finally, as shown in FIG. 1, the source electrode 39, the drain electrode 40. Base electrode 41. A collector electrode 42 is formed at the same time. In the steps shown in FIGS. 2 to 9, the n buried portion 22 of the bipolar transistor and the n ten buried portion 21 of the MOS transistor. Although the steps for forming the collector contact 34 of the bipolar transistor in the p-type substrate 20 and the n+ region are not shown.
通常の方法で簡単に形成することができる。ゲート電極
３６とソース、ドレイン電極３９．４０は２層構造に、
エミッタ電極３Ｔとベース電極４１は２層構造になる。It can be easily formed using conventional methods. The gate electrode 36 and the source and drain electrodes 39 and 40 have a two-layer structure,
The emitter electrode 3T and the base electrode 41 have a two-layer structure.
発明の効果
以上述べてきたように本発明によれば、簡易な構造で高
性能のＭＯＳトランジスタと高速のバイポーラトランジ
スタを互いの性能を損うことなく一体化することができ
、実用上きわめて有用である。Effects of the Invention As described above, according to the present invention, it is possible to integrate a high-performance MOS transistor and a high-speed bipolar transistor with a simple structure without degrading each other's performance, which is extremely useful in practice. be.
第１図は本発明の一実施例における半導体集積回路装置
の断面図、第２図〜第９図は上記半導体集積回路装置の
製造プロセスを説明するだめの断面図、第１０図は従来
の半導体集積回路装置を示す断面図である。
３６・・・・・・ゲート電極、３７・・・・・・エミッ
タ電極。
３８・・・・・・多層用の眉間絶縁膜、３９・・・・・
・ソース電極、４０・・・・・・ドレイン電極、４１・
・・・・・ベース電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
３ｔ−−−ｐ秀■帆、ｔｔｒイＡ７−ラー２１１ｐτ−
人 ４ｊ−７４ドラシア−ＩＬ第２図
第１０因FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIGS. 2 to 9 are cross-sectional views for explaining the manufacturing process of the semiconductor integrated circuit device, and FIG. 10 is a conventional semiconductor integrated circuit device. FIG. 1 is a cross-sectional view showing an integrated circuit device. 36...Gate electrode, 37...Emitter electrode. 38...Multilayer glabella insulating film, 39...
・Source electrode, 40...Drain electrode, 41・
...Base electrode. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 3t---p Hide ■ sail, ttri A7-ra 211p
Person 4j-74 Dorashia-IL Figure 2 Factor 10
Claims (1)
電極、バイポーラトランジスタのエミッタ電極と、上記
ゲート電極とエミッタ電極上を被覆する絶縁膜と、上記
絶縁膜をそれぞれ開口して形成されたソース、ドレイン
電極及びベース電極を備えたことを特徴とする半導体集
積回路装置。A gate electrode of a MOS transistor, an emitter electrode of a bipolar transistor formed in the same process, an insulating film covering the gate electrode and the emitter electrode, and a source and drain electrode formed by opening the insulating film, respectively. A semiconductor integrated circuit device comprising a base electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP106785A JPS61160965A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP106785A JPS61160965A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61160965A true JPS61160965A (en) | 1986-07-21 |
Family
ID=11491182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP106785A Pending JPS61160965A (en) | 1985-01-08 | 1985-01-08 | Semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61160965A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63179564A (en) * | 1987-01-21 | 1988-07-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS63244768A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Bipolar cmos type semiconductor device and manufacture thereof |
| JPS63283152A (en) * | 1987-05-15 | 1988-11-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63284854A (en) * | 1987-05-18 | 1988-11-22 | Seiko Epson Corp | Semiconductor device and its manufacture |
| FR2626406A1 (en) * | 1988-01-22 | 1989-07-28 | France Etat | Bipolar transistor compatible with MOS technology |
-
1985
- 1985-01-08 JP JP106785A patent/JPS61160965A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63179564A (en) * | 1987-01-21 | 1988-07-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS63244768A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Bipolar cmos type semiconductor device and manufacture thereof |
| JPS63283152A (en) * | 1987-05-15 | 1988-11-21 | Toshiba Corp | Semiconductor device and manufacture thereof |
| JPS63284854A (en) * | 1987-05-18 | 1988-11-22 | Seiko Epson Corp | Semiconductor device and its manufacture |
| FR2626406A1 (en) * | 1988-01-22 | 1989-07-28 | France Etat | Bipolar transistor compatible with MOS technology |
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