JPH10270683A - Semiconductor device and its manufacture - Google Patents
Semiconductor device and its manufactureInfo
- Publication number
- JPH10270683A JPH10270683A JP9071176A JP7117697A JPH10270683A JP H10270683 A JPH10270683 A JP H10270683A JP 9071176 A JP9071176 A JP 9071176A JP 7117697 A JP7117697 A JP 7117697A JP H10270683 A JPH10270683 A JP H10270683A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- trench
- impurity concentration
- semiconductor device
- high impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 45
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000012535 impurity Substances 0.000 claims abstract description 68
- 230000003647 oxidation Effects 0.000 claims abstract description 40
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 40
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 28
- 239000010703 silicon Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 8
- 229910052787 antimony Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 6
- 230000001629 suppression Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 229920005591 polysilicon Polymers 0.000 description 12
- 229910004298 SiO 2 Inorganic materials 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000005259 measurement Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は半導体装置及びその
製造方法に係り、特にU−MOSFET等のトレンチゲ
ートを有する半導体装置のゲート電極引き出し部に適用
されるものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a trench gate, such as a U-MOSFET, applied to a gate electrode lead-out portion.
【0002】[0002]
【従来の技術】従来のトレンチゲートを有する半導体装
置のゲート引き出し部は、トレンチ開口周辺のエッジ部
分において前記ゲート引き出し部を絶縁する熱酸化膜に
電界集中を生じ、ゲート耐圧が低下するという問題があ
った。図7(a)は従来のゲート引き出し部の構造を示
す平面図、図7(b)はそのB一B断面図である。2. Description of the Related Art A conventional gate lead portion of a semiconductor device having a trench gate has a problem that an electric field is concentrated on a thermal oxide film that insulates the gate lead portion at an edge portion around a trench opening, thereby lowering a gate breakdown voltage. there were. FIG. 7A is a plan view showing the structure of a conventional gate lead-out portion, and FIG. 7B is a sectional view taken along the line B-B.
【0003】この半導体装置は、n+ 半導体基板1、n
- エピタキシャル層2、pベース層3、n+ ソース高不
純物濃度層4、トレンチ5、熱酸化膜6、トレンチに埋
め込まれたポリシリコン7、ゲートパッド8、ゲートパ
ッド8を金属配線に接続するコンタクトホール9からな
っている。ここに熱酸化膜6は、トレンチ5の内部にお
いてU−MOSFETのゲート絶縁膜となる領域を含め
て、露出したシリコンの全表面を熱酸化することにより
一度に形成される。なお図7(a)の平面図には熱酸化
膜6は示されていない。This semiconductor device has an n + semiconductor substrate 1, n
- contact epitaxial layer 2, p base layer 3, n + source high impurity concentration layer 4, the trench 5, the thermal oxide film 6, the polysilicon 7 buried in the trench, the gate pad 8, the gate pad 8 is connected to the metal wiring It consists of Hall 9. Here, the thermal oxide film 6 is formed at a time by thermally oxidizing the entire surface of the exposed silicon, including the region serving as the gate insulating film of the U-MOSFET inside the trench 5. Note that the thermal oxide film 6 is not shown in the plan view of FIG.
【0004】前記トレンチゲートを有する半導体装置
は、n+ 半導体基板1をドレイン、n+ 高不純物濃度層
4をソース、及びトレンチに埋め込まれたポリシリコン
7を表面上に引き出すゲートパッド8をゲート電極と
し、トレンチ5の側壁をnチャネルとするU−MOSF
ETとして動作する。In the semiconductor device having the trench gate, an n + semiconductor substrate 1 is used as a drain, an n + high impurity concentration layer 4 is used as a source, and a gate pad 8 for extracting polysilicon 7 buried in the trench to the surface is used as a gate electrode. U-MOSF having the side wall of the trench 5 as an n-channel
Operate as ET.
【0005】図7(b)の円内に示すように、トレンチ
5の内部からポリシリコン7を引き出す部分において、
熱酸化膜6の形成の際発生する応力により下地シリコン
のトレンチ開口周辺に尖りを生じる。この尖り部分で熱
酸化膜6の厚さが薄くなり、ゲート・ソース間に電圧が
印加されれば、前記尖り部分に電界集中を生じてゲート
耐圧が低下する。As shown in the circle of FIG. 7B, at the portion where the polysilicon 7 is drawn from the inside of the trench 5,
The stress generated during the formation of the thermal oxide film 6 causes sharpness around the trench opening of the underlying silicon. If the thermal oxide film 6 becomes thin at the sharp portion and a voltage is applied between the gate and the source, an electric field concentration occurs at the sharp portion and the gate breakdown voltage decreases.
【0006】またソース領域となる4がゲートパッド8
の下部にまで延長されれば、ゲート電位の影響によりゲ
ートパッド8の下部にn型表面チャネルを形成し易くな
り、U−MOSFETのチャネルリークが増加するとい
う問題があった。The source region 4 is a gate pad 8
, It is easy to form an n-type surface channel under the gate pad 8 due to the influence of the gate potential, and there is a problem that the channel leakage of the U-MOSFET increases.
【0007】このため、U−MOSFETのソース領域
となる4と前記表面チャネルとの導通をさけるよう、図
7(a)に示すように、4の右端とゲートパッド8の左
端との間のトレンチ引き出し部には前記n+ 高不純物濃
度層4を形成しない構造とされていた。For this reason, as shown in FIG. 7A, a trench between the right end of 4 and the left end of gate pad 8 is provided to prevent conduction between the source region 4 of the U-MOSFET and the surface channel. The lead portion has a structure in which the n + high impurity concentration layer 4 is not formed.
【0008】[0008]
【発明が解決しようとする課題】上記したように従来の
トレンチゲートを有する半導体装置は、ゲート電極引き
出し部のトレンチ開口周辺のエッヂ部分に電界集中を生
じてゲート耐圧が低下し、またゲートパッドの下部に表
面チャネルを形成し易く、これがU−MOSFETのソ
ース拡散層と導通することによりチャネルリークの増加
を招くという問題があった。As described above, in the conventional semiconductor device having a trench gate, an electric field concentration occurs at an edge portion around a trench opening of a gate electrode lead-out portion, so that a gate breakdown voltage is reduced and a gate pad is not provided. There is a problem that a surface channel is easily formed in the lower portion, and this causes conduction with the source diffusion layer of the U-MOSFET, thereby causing an increase in channel leakage.
【0009】本発明は上記の問題点を解決すべくなされ
たもので、ゲート耐圧が高く、かつチャネルリークの小
さいトレンチゲートを有する半導体装置とその製造方法
を提供することを目的とする。The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device having a trench gate having a high gate breakdown voltage and a small channel leak, and a method of manufacturing the same.
【0010】[0010]
【課題を解決するための手段】本発明の半導体装置は、
シリコン基板上に形成された少なくとも1層の第1導電
型のドレイン層と、ドレイン層上に積層された第2導電
型のベース層と、このベース層を貫通し、ドレイン層に
達するトレンチと、ゲートパッドの下部においてトレン
チの開口周辺に前記ベース層の厚さより浅く形成された
増速酸化に役立つ高不純物濃度層と、トレンチの内部表
面を含むシリコン表面を覆う熱酸化膜とを備え、増速酸
化に役立つ高不純物濃度層により、トレンチの開口周辺
のエッジ部分における熱酸化膜の膜厚が、平面上の膜厚
と同等にされたことを特徴とする。According to the present invention, there is provided a semiconductor device comprising:
At least one drain layer of the first conductivity type formed on the silicon substrate, a base layer of the second conductivity type stacked on the drain layer, a trench penetrating the base layer and reaching the drain layer; A high-impurity-concentration layer formed at a lower portion of the gate pad around the opening of the trench to be shallower than the thickness of the base layer and serving as a speed-up oxidation, and a thermal oxide film covering a silicon surface including an inner surface of the trench; The thickness of the thermal oxide film at the edge portion around the opening of the trench is made equal to the thickness on the plane by the high impurity concentration layer useful for oxidation.
【0011】好ましくは本発明の半導体装置は、前記高
不純物濃度層に添加する不純物が少なくともP、As、
Sb及びBのいずれか1つを含むことを特徴とする。ま
た好ましくは、前記高不純物濃度層が電気的にフローテ
ィングとされたことを特徴とする。Preferably, in the semiconductor device of the present invention, the impurity added to the high impurity concentration layer is at least P, As,
It is characterized by containing one of Sb and B. Preferably, the high impurity concentration layer is electrically floating.
【0012】さらに好ましくは本発明の半導体装置は、
前記第2導電型のベース層が少なくともゲートパッドの
下部において、第2導電型の不純物が高濃度に添加され
たものであることを特徴とする。[0012] More preferably, the semiconductor device of the present invention comprises:
The second conductive type base layer is characterized in that a second conductive type impurity is added at a high concentration at least below the gate pad.
【0013】またさらに好ましくは本発明の半導体装置
は、前記第2導電型のベース層が少なくともゲートパッ
ドの下部において、第2導電型の不純物が高濃度に添加
されたウエル領域を含むことを特徴とする。Still more preferably, in the semiconductor device of the present invention, the base layer of the second conductivity type includes a well region, at least below the gate pad, in which impurities of the second conductivity type are added at a high concentration. And
【0014】本発明の半導体装置の製造方法は、シリコ
ン基板上に少なくとも1層の第1導電型のドレイン層を
形成し、ドレイン層上に隣接して第2導電型のベース層
を形成し、前記ベース層表面の内、少なくともゲートパ
ッドの下部において、トレンチの開口位置を規定するト
レンチパターン内とその周辺領域に、少なくともP、A
S、Sb及びBのいずれか1つを選択拡散又はイオン注
入することにより、増速酸化に役立つ高不純物濃度層を
前記ベース層の厚さより浅く形成し、この高不純物濃度
層と前記ベース層とを貫通して前記ドレイン層に達する
トレンチを、トレンチパターンにより形成されたエッチ
ングマスクを用いて異方性エッチングすることにより形
成し、前記トレンチの内部表面を含むシリコン表面を熱
酸化することにより、トレンチの開口周辺に残された増
速酸化に役立つ高不純物濃度層により、トレンチの開口
周辺のエッジ部分における熱酸化膜の膜厚が平面上の膜
厚と同等になるようにすることを特徴とする。According to a method of manufacturing a semiconductor device of the present invention, at least one first conductivity type drain layer is formed on a silicon substrate, and a second conductivity type base layer is formed adjacent to the drain layer. At least P, A in the trench pattern defining the opening position of the trench and its peripheral region at least below the gate pad on the surface of the base layer.
By selectively diffusing or ion-implanting any one of S, Sb and B, a high impurity concentration layer useful for accelerated oxidation is formed shallower than the thickness of the base layer. Forming a trench that reaches the drain layer through anisotropic etching using an etching mask formed by a trench pattern, and thermally oxidizing a silicon surface including an inner surface of the trench, thereby forming a trench. Characterized in that the thickness of the thermal oxide film at the edge portion around the opening of the trench is made equal to the thickness on the plane by the high impurity concentration layer useful for the accelerated oxidation left around the opening. .
【0015】好ましくは本発明の製造方法は、高不純物
濃度層の周辺が全て第2導電型のベース層で囲まれるよ
うにパターン形成されたものであることを特徴とする。
さらに好ましくは本発明の製造方法は、第2導電型のベ
ース層の内少なくとも前記ゲートパッドの下部領域に、
第2導電型の不純物を選択拡散又はイオン注入すること
により高不純物濃度のウエル領域を形成することを特徴
とする。Preferably, the manufacturing method according to the present invention is characterized in that the high impurity concentration layer is patterned so that the entire periphery is surrounded by a second conductivity type base layer.
More preferably, the manufacturing method according to the present invention further comprises the step of:
A well region having a high impurity concentration is formed by selectively diffusing or ion-implanting an impurity of the second conductivity type.
【0016】[0016]
【発明の実施の形態】以下、図面を参照して本発明の実
施の形態を詳細に説明する。図1は、本発明の第1の実
施の形態に係るU−MOSFETからなる半導体装置の
構造を示す平面図と断面図である。図1(a)は平面
図、図1(b)はそのA−A断面を示す。図の参照番号
は図2に対応して付与しているため説明を省略する。Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a plan view and a cross-sectional view illustrating a structure of a semiconductor device including a U-MOSFET according to a first embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along the line AA. Reference numerals in the figure are given in correspondence with FIG.
【0017】図7に示す従来のU−MOSFETからな
る半導体装置との相違は、U−M0SFETのソースと
なるn+ 高不純物濃度層4を形成する際、同時にゲート
パッド8の下部のゲート引き出し部にn+ 高不純物濃度
層4aを形成することにある。The difference from the conventional U-MOSFET semiconductor device shown in FIG. 7 is that when the n + high impurity concentration layer 4 serving as the source of the U-M0SFET is formed, the gate lead portion under the gate pad 8 is simultaneously formed. To form an n + high impurity concentration layer 4a.
【0018】前述したように図7に示す従来のU−MO
SFETは、ゲートパッド8の下部のゲート引き出し部
において、下地シリコンに形成したトレンチ開口周辺の
エッジ部分に尖りを生じ、この尖り部分で熱酸化膜6の
厚さが薄くなり、ここに電界集中を生じることによりゲ
ート・ソース間耐圧が大幅に低下する。As described above, the conventional U-MO shown in FIG.
In the SFET, in the gate lead-out portion below the gate pad 8, sharp edges are formed around the trench openings formed in the underlying silicon, and the thickness of the thermal oxide film 6 is reduced at these sharp portions, and the electric field concentration is reduced there. As a result, the withstand voltage between the gate and the source is greatly reduced.
【0019】熱酸化膜6は、下地シリコンに設けたトレ
ンチ5の内壁とpベース層3を含むシリコン表面とを熱
酸化することにより形成される。前記尖り形状は、シリ
コン基板の熱酸化過程により誘起された熱酸化膜中の応
力により、トレンチ開口周辺のエッジ部分における酸化
速度が抑制されることにより生じる。The thermal oxide film 6 is formed by thermally oxidizing the inner wall of the trench 5 provided in the underlying silicon and the silicon surface including the p base layer 3. The sharpened shape is caused by the suppression of the oxidation rate at the edge portion around the trench opening due to the stress in the thermal oxide film induced by the thermal oxidation process of the silicon substrate.
【0020】このエッジ部分の形状を改善するため、前
記熱酸化膜中の応力による下地シリコンの酸化速度の抑
制に対して、逆にエッジ部分において下地シリコンの酸
化速度を増加する増速酸化作用を有する高不純物濃度層
を導入する。In order to improve the shape of the edge portion, the accelerated oxidation effect of increasing the oxidation rate of the underlying silicon at the edge portion is contrary to the suppression of the oxidation rate of the underlying silicon due to the stress in the thermal oxide film. A high impurity concentration layer is introduced.
【0021】シリコン基板上のpベース層表面の増速酸
化は、n型不純物としてpベース層に高濃度のPやAs
を導入し熱酸化することにより生じる。従って、図1
(a)の左側のU−MOSFETのソース領域となるn
+ 高不純物濃度層4の形成と同時に、増速酸化用のn+
高不純物濃度層4aを形成する。図1(a)の右側に示
す増速酸化用n+ 高不純物濃度層4aは、ソース領域と
なるn+ 高不純物濃度層4を単にパターン変更すること
により、同一拡散工程で同時に形成することができる。The accelerated oxidation of the surface of the p base layer on the silicon substrate is performed by adding a high concentration of P or As to the p base layer as an n-type impurity.
And thermal oxidation. Therefore, FIG.
N which is the source region of the U-MOSFET on the left side of FIG.
+ Simultaneously with the formation of the high impurity concentration layer 4, n +
The high impurity concentration layer 4a is formed. The n + high impurity concentration layer 4a for enhanced oxidation shown on the right side of FIG. 1A can be formed simultaneously in the same diffusion step by simply changing the pattern of the n + high impurity concentration layer 4 serving as the source region. it can.
【0022】図1(a)、図1(b)に示すように、ゲ
ート電極引き出し用トレンチ5の開口周辺に増速酸化用
のn+ 高不純物濃度層4aを形成した後、熱酸化法によ
り熱酸化膜6を形成すれば、図1(b)の円内に示すよ
うに、4aの増速酸化作用によりトレンチ5の開口周辺
のエッジ部分は完全に角がとれた形状にすることができ
る。As shown in FIGS. 1 (a) and 1 (b), after forming an n + high impurity concentration layer 4a for speed-up oxidation around the opening of the trench 5 for leading out the gate electrode, a thermal oxidation method is used. If the thermal oxide film 6 is formed, as shown in the circle of FIG. 1B, the edge portion around the opening of the trench 5 can be made completely rounded by the accelerated oxidation action of 4a. .
【0023】従ってゲート・ソース間耐圧のクリティカ
ルパスとなる、ゲート電極引き出し用トレンチ5のエッ
ジ部分における熱酸化膜6の厚さを、下地シリコンの平
面上に形成された熱酸化膜6の厚さとほぼ同等にするこ
とができ、従来問題であったトレンチ開口周辺のエッジ
の尖り部分における電界集中を除去することができる。Therefore, the thickness of the thermal oxide film 6 at the edge of the gate electrode leading-out trench 5, which is a critical path for the gate-source breakdown voltage, is set to the thickness of the thermal oxide film 6 formed on the plane of the underlying silicon. Thus, the electric field concentration at the sharp edge portion around the trench opening, which has conventionally been a problem, can be eliminated.
【0024】また本第1の実施の形態において、図1
(a)に示すように、U−MOSFETのソースとなる
n+ 高膿度不純物層4と、増速酸化用のn+ 高不純物濃
度層4aとはpベース層3により分離されている。前述
したように4aはソースとなる4と同時に形成されるた
め、4aの層の厚さはpベース層3の厚さより小さい。
従ってn+ 型の4aは、その周辺と底面が全てpベース
層で囲まれ、かつトレンチ5に埋め込まれたポリシリコ
ン7との間は熱酸化膜6で絶縁されているため、電気的
にフローティングとなり、U−MOSFETのチャネル
リークを低減する効果がある。In the first embodiment, FIG.
As shown in (a), the n + high impurity concentration impurity layer 4 serving as the source of the U-MOSFET and the n + high impurity concentration layer 4a for the speed-up oxidation are separated by the p base layer 3. As described above, the layer 4a is formed at the same time as the source 4, so that the thickness of the layer 4a is smaller than the thickness of the p base layer 3.
Therefore, the n @ + type 4a is electrically floating because its periphery and bottom surface are all surrounded by the p base layer and the polysilicon 7 buried in the trench 5 is insulated by the thermal oxide film 6. This has the effect of reducing the channel leakage of the U-MOSFET.
【0025】図1のn+ 高不純物濃度層4aを導入する
ことによるゲート・ソース間耐圧の向上効果を図2に示
す。図の横軸はゲート・ソース間電圧VGSS(V)、
縦軸はゲート・ソース間電流IGSS(A)、熱酸化膜
6の厚さToxは50nmである。従来に比べてゲート・
ソース間耐圧が大幅に向上することがわかった。FIG. 2 shows the effect of improving the gate-source withstand voltage by introducing the n + high impurity concentration layer 4a of FIG. The horizontal axis in the figure is the gate-source voltage VGSS (V),
The vertical axis indicates the gate-source current IGSS (A), and the thickness T ox of the thermal oxide film 6 is 50 nm. Gate and gate
It was found that the source-to-source breakdown voltage was greatly improved.
【0026】次に本発明の第2の実施の形態について説
明する。第2の実施の形態においては、前記n+ 高不純
物濃度層4aを有する図1に示す構造に加えて、ゲート
パッド8の下部において従来1017cm-3〜1018cm
-3であったp型ベース層3の正孔濃度を1018cm-3〜
1020cm-3とp+ 型に高めることにより、p+ 型ベー
ス層3の表面のn型反転層の生成を抑制することに特徴
がある。Next, a second embodiment of the present invention will be described. In the second embodiment, in addition to the structure shown in FIG. 1 having the n @ + high impurity concentration layer 4a, the conventional structure at the lower portion of the gate pad 8 is 10 @ 17 cm @ -3 to 10 @ 18 cm.
The hole concentration of the p-type base layer 3, which was -3 , was 10 18 cm -3 or less .
By increasing the p + -type to 10 20 cm −3 , generation of an n-type inversion layer on the surface of the p + -type base layer 3 is suppressed.
【0027】このようにn型反転層の生成が抑制されれ
ば、前述のようにU−MOSFETのチャネルリークの
増加を抑制することができる。本第2の実施の形態と図
7の従来構造の最良のU−MOSFETについて、ドレ
イン電流IDSのドレイン電圧VDS依存性を対比して
図3に示す。If the formation of the n-type inversion layer is suppressed as described above, it is possible to suppress an increase in channel leak of the U-MOSFET as described above. FIG. 3 shows a comparison between the drain voltage VDS and the drain current IDS of the best U-MOSFET of the second embodiment and the conventional structure of FIG.
【0028】測定に用いたU−MOSFETの各部の寸
法、抵抗値、測定条件等は、p型ベース拡散層の深さX
jbase =2μm、トレンチの深さ=3μm、ゲート酸化
膜の厚さTox=50nm、n- エピタキシャル層2の厚
さTVG=8μm、比抵抗ρVG=0.8Ωcm、VGS=
0Vであった。なお、ゲート・ソース間耐圧については
図2と同様な結果が得られている。The dimensions, resistance values, measurement conditions, etc. of each part of the U-MOSFET used for the measurement are determined by the depth X of the p-type base diffusion layer.
jbase = 2 μm, trench depth = 3 μm, gate oxide film thickness T ox = 50 nm, n − epitaxial layer 2 thickness T VG = 8 μm, specific resistance ρ VG = 0.8 Ωcm, VGS =
It was 0V. It should be noted that the same result as in FIG. 2 was obtained for the gate-source withstand voltage.
【0029】図3からn+ 高不純物濃度層4aを設けて
も、チャネルリークの値は従来の4aがない最良の結果
に比べてほとんど遜色がないことがわかる。従ってn+
高不純物濃度層4aを形成し、かつゲートパッド8の下
部におけるpベース層3の正孔濃度を高くすることによ
り、ドレイン・ソース間のリーク電流すなわちチャネル
リークに何等悪影響を生じることなく、ゲート・ソース
間耐圧を大幅に向上することができる。FIG. 3 shows that even if the n + high impurity concentration layer 4a is provided, the channel leak value is almost equal to the best result without the conventional 4a. Therefore n +
By forming the high impurity concentration layer 4a and increasing the hole concentration of the p base layer 3 under the gate pad 8, the leakage current between the drain and the source, that is, the channel leakage is not adversely affected. The withstand voltage between sources can be greatly improved.
【0030】次に図4(a)に基づき本発明の第3の実
施の形態について説明する。図4(a)は前記第1の実
施の形態の変形例である。図1(a)、図1(b)に示
すゲートパッド8に正のゲート電圧を印加すれば、下地
シリコン1の表面にn型表面チャネルを生じやすい。こ
のn型表面チャネルがゲートパッド8の外部に拡大して
図1(a)のC−Cの境界を越えれば、n+ ソース領域
4とn+ 高不純物濃度層4aとが前記n型表面チャネル
で接続され、U−MOSFETのチャネルリークを増大
させる。Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 4A is a modification of the first embodiment. When a positive gate voltage is applied to the gate pad 8 shown in FIGS. 1A and 1B, an n-type surface channel is easily generated on the surface of the underlying silicon 1. If the n-type surface channel extends outside the gate pad 8 and exceeds the boundary of C-C in FIG. 1A, the n + source region 4 and the n + high impurity concentration layer 4a are connected to the n-type surface channel. To increase the channel leakage of the U-MOSFET.
【0031】前記第2の実施の形態において、pベース
層3全体の正孔濃度を高くすることにより前記n型表面
反転層の生成を抑制した。しかしこのとき同時にU−M
OSFETに含まれる漂遊容量の増大等、動作特性上好
ましくない問題を生じることがある。In the second embodiment, the generation of the n-type surface inversion layer is suppressed by increasing the hole concentration of the entire p base layer 3. However, at this time, UM
Problems such as an increase in stray capacitance included in the OSFET and unfavorable operation characteristics may occur.
【0032】第3の実施の形態ではこの問題を回避する
ため、pベース層全体を高不純物濃度とすることをさ
け、図4(a)に示すようにチャネルストップ用のp+
ウエル4bを設けることにより、前記n型表面チャネル
がC−Cを越えて4と4aとが接続されるのを防止す
る。[0032] Since in the third embodiment to avoid this problem, avoid that the high impurity concentration across the p-base layer, a channel stop, as shown in FIG. 4 (a) p +
The provision of the well 4b prevents the n-type surface channel from connecting between 4 and 4a beyond CC.
【0033】p+ ウエル4bの配置は、図1(a)のC
−Cの右側のゲートパッド8の下部において、全てのn
+ 高不純物濃度層4aを一括して取り囲むものであって
もよいし、ゲートパッド8の外部において、ゲートパッ
ド8を取り囲むようにしてもよい。またC−Cの境界線
に沿って配置するだけでも大きな効果が得られる。The arrangement of the p + well 4b is as shown in FIG.
Under the gate pad 8 on the right side of -C, all n
+ The high impurity concentration layer 4a may be surrounded at a time, or may be surrounded outside the gate pad 8 around the gate pad 8. In addition, a great effect can be obtained simply by arranging along the boundary of C-C.
【0034】一例として図4(a)では、図1(a)に
示すゲートパッド8の縁に沿ってこれを取り囲むよう
に、前記p+ ウエル4bを形成した場合の断面図が示さ
れている。このときゲートパッド8の右側の縁は、ソー
ス領域4と対向していないので、p+ ウエル4bの形成
を省略することができる。またp+ ウエル4bは図4
(a)において、前述のように全体がゲートパッド8の
下部になるように配置してもよい。このようにすればチ
ップ面積を低減する上で効果がある。As an example, FIG. 4A shows a cross-sectional view of the case where the p + well 4b is formed along the edge of the gate pad 8 shown in FIG. 1A so as to surround it. . At this time, since the right edge of the gate pad 8 does not face the source region 4, the formation of the p + well 4b can be omitted. P + well 4b is shown in FIG.
In (a), as described above, the entire structure may be arranged so as to be below the gate pad 8. This is effective in reducing the chip area.
【0035】次に図4(b)に基づき、本発明の第4の
実施の形態について説明する。第4の実施の形態に係る
半導体装置は、前述の増速酸化作用が必ずしもP、A
s、Sbのようなn型不純物を添加したn+ 型高不純物
濃度層ばかりでなく、B(硼素)のようなp型不純物を
添加したp+ 型高不純物濃度層にもみられることに基づ
くものである。Next, a fourth embodiment of the present invention will be described with reference to FIG. In the semiconductor device according to the fourth embodiment, the aforementioned accelerated oxidation action is not necessarily P, A
This is based on the fact that it is found not only in an n + -type high impurity concentration layer to which an n-type impurity such as s and Sb is added, but also in a p + -type high impurity concentration layer to which a p-type impurity such as B (boron) is added. It is.
【0036】図4(b)に示すように、図1(b)のn
+ 型高不純物濃度層4aのかわりに、p+ 高不純物濃度
層4cをトレンチ5の開口周辺領域に形成することによ
り、前記開口周辺のエッジ部分の尖りを除去しゲート耐
圧を向上することができる。As shown in FIG. 4B, n in FIG.
By forming the p + high impurity concentration layer 4c in the region around the opening of the trench 5 instead of the + type high impurity concentration layer 4a, the sharpness of the edge portion around the opening can be removed and the gate breakdown voltage can be improved. .
【0037】このように増速酸化用の高濃度不純物層を
p+ 型とすれば、n+ 型ソース領域と同時に同一工程で
増速酸化用の高濃度不純物層を形成する利点は失われる
が、第2、第3の実施の形態にのべたゲートパッド8の
下部における下地シリコンの表面反転層形成の問題が解
消されるという大きな利点がある。If the high-concentration impurity layer for accelerated oxidation is p + -type, the advantage of forming the high-concentration impurity layer for accelerated oxidation in the same step simultaneously with the n + -type source region is lost. The second and third embodiments have a great advantage that the problem of the formation of the surface inversion layer of the underlying silicon under the solid gate pad 8 can be solved.
【0038】次に本発明の第5の実施の形態に係る本発
明の半導体装置の製造方法について工程順に説明する。
図5、図6に基づき本発明の第1の実施の形態に係る半
導体装置の製造方法についてのべる。Next, a method of manufacturing a semiconductor device according to a fifth embodiment of the present invention will be described in the order of steps.
The method for manufacturing the semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS.
【0039】図5(a)に示すように、n+ シリコン基
板1の上にn- 層2をエピタキシャル成長し、B拡散に
よりpベース層3を形成する。次に図5(b)に示すよ
うに、不純物拡散用のSiO2 マスクパターン10を用
いて例えばAsを選択的に拡散し、U−MOSFETの
ソース領域となるn+ 高不純物濃度層4と、増速酸化用
のn+ 高不純物濃度層4aを同時に形成する。As shown in FIG. 5A, an n - layer 2 is epitaxially grown on an n + silicon substrate 1, and a p base layer 3 is formed by B diffusion. Next, as shown in FIG. 5B, for example, As is selectively diffused using an SiO 2 mask pattern 10 for impurity diffusion, and an n + high impurity concentration layer 4 serving as a source region of the U-MOSFET is formed. An n + high impurity concentration layer 4a for accelerated oxidation is simultaneously formed.
【0040】図5(b)では本発明に直接関連する増速
酸化用のn+ 高不純物濃度層4aを形成する領域の工程
断面図が示されている。このときAs拡散により形成さ
れる前記n+ 高不純物濃度層4と4aの厚さは、pベー
ス層3の厚さより小さくなるように設定される。FIG. 5B is a process sectional view showing a region for forming an n + high impurity concentration layer 4a for accelerated oxidation, which is directly related to the present invention. At this time, the thickness of the n + high impurity concentration layers 4 and 4a formed by As diffusion is set to be smaller than the thickness of the p base layer 3.
【0041】マスクパターンを除去した後、図5(c)
に示すように、トレンチの形成部分にRIE(Reactive
Ion Etching)用のエッチングマスク11を形成し、前
記RIE法により前記n+ 高不純物濃度層4と4a及び
前記pベース層3を貫通して前記n- エピタキシャル層
2に達するトレンチ5を形成する。After removing the mask pattern, FIG.
As shown in FIG. 3, RIE (Reactive
An etching mask 11 for ion etching is formed, and a trench 5 penetrating through the n + high impurity concentration layers 4 and 4a and the p base layer 3 and reaching the n - epitaxial layer 2 is formed by the RIE method.
【0042】次に図6(d)に示すように、RIE用の
エッチングマスクを除去して表面を露出し、通常の熱酸
化法を用いてトレンチ5の内部表面を含む下地シリコン
の全表面に熱酸化膜6を形成する。Next, as shown in FIG. 6D, the etching mask for RIE is removed to expose the surface, and the entire surface of the underlying silicon including the inner surface of the trench 5 is formed using a normal thermal oxidation method. A thermal oxide film 6 is formed.
【0043】この工程により、前記トレンチ5の内部表
面に形成された熱酸化膜6の内、図1(a)の左側のC
−Cの左側にあるものはU−MOSFETのポリシリコ
ンゲート7とpベース層3との間のゲート絶縁膜とな
り、C−Cの右側にあるものはゲート引き出し用ポリシ
リコン7とpベース層とを絶縁する絶縁膜6となる。By this step, of the thermal oxide film 6 formed on the inner surface of the trench 5, C on the left side of FIG.
The one on the left side of -C is a gate insulating film between the polysilicon gate 7 of the U-MOSFET and the p base layer 3, and the one on the right side of C-C is the gate drawing polysilicon 7 and the p base layer. Becomes an insulating film 6 for insulating the substrate.
【0044】上記熱酸化工程において、図1(b)の円
内と図6の各工程断面図に示されるように、n+ 高不純
物濃度層4aが増速酸化層として作用し、ゲート引き出
し部のトレンチ開口部周辺のエッジが除去されることに
より、前記エッジ部分の熱酸化膜6の厚さを、下地シリ
コンの平面上における熱酸化膜の厚さと同等にすること
ができる。In the above-described thermal oxidation step, as shown in the circle of FIG. 1B and the cross-sectional views of each step of FIG. 6, the n + high impurity concentration layer 4a acts as a speed-up oxidation layer, By removing the edge around the trench opening, the thickness of the thermal oxide film 6 at the edge portion can be made equal to the thickness of the thermal oxide film on the plane of the underlying silicon.
【0045】図6(e)に示すように、導電性ポリシリ
コン層7を堆積後エッチバックする公知の方法によりポ
リシリコン7を前記トレンチ5に埋め込み、パターニン
グによりポリシリコンゲートパッド8と前記ポリシリコ
ン7とを一体のものとして形成する。As shown in FIG. 6E, a polysilicon 7 is buried in the trench 5 by a known method of depositing a conductive polysilicon layer 7 and then etching back, and a polysilicon gate pad 8 and the polysilicon are formed by patterning. 7 are formed as one body.
【0046】次に図6(f)に示すように、CVD法に
より全面にSiO2 膜12を形成し、このSiO2 にコ
ンタクトホール9を開孔してゲートパッド8と金属配線
13とを接続する。同様にソースn+ 拡散層4、及びド
レインとなるn+ 基板1にそれぞれ金属配線を接続し
(図示されていない)、第1の実施の形態の半導体装置
を完成する。Next, as shown in FIG. 6F, a SiO 2 film 12 is formed on the entire surface by the CVD method, and a contact hole 9 is opened in the SiO 2 to connect the gate pad 8 and the metal wiring 13. I do. Similarly, metal wirings (not shown) are connected to the source n + diffusion layer 4 and the n + substrate 1 serving as the drain, respectively, to complete the semiconductor device of the first embodiment.
【0047】第2、第3の実施の形態に係る半導体装置
の製造方法は、Bを選択的に拡散することにより、ゲー
トパッド8を形成する領域のpベース層8を高濃度のp
型にするか、又はチャネルストップ用p+ ウエル4bを
形成するほかは、前記第1の実施の形態の製造方法と同
様である。このとき前記pベース層8を高濃度のp型に
する工程は、必ずしも深さ方向についてpベース層3全
体を高濃度にする必要はなく、その表面のみにp+ 拡散
を行ってもよい。In the manufacturing method of the semiconductor device according to the second and third embodiments, by selectively diffusing B, the p base layer 8 in the region where the gate pad 8 is to be formed has a high concentration of p.
The method is the same as the manufacturing method of the first embodiment except that a mold or a channel stop p + well 4b is formed. At this time, in the step of making the p base layer 8 a high concentration p-type, it is not always necessary to make the entire p base layer 3 high concentration in the depth direction, and p + diffusion may be performed only on the surface thereof.
【0048】第4の実施の形態に係る半導体装置の製造
方法は、前述のように図1(a)に示すソースn+ 拡散
層4と図4(b)に示す増速酸化用p+ 拡散層4cとを
同時に形成することができず、前記4cの形成を別工程
としなければならない。このほかは前記第1の実施の形
態の製造方法と同様である。As described above, the method of manufacturing the semiconductor device according to the fourth embodiment includes the source n + diffusion layer 4 shown in FIG. 1A and the p + diffusion for accelerated oxidation shown in FIG. The layer 4c cannot be formed at the same time, and the formation of the layer 4c must be performed in a separate step. The other points are the same as those in the manufacturing method of the first embodiment.
【0049】なお本発明は上記の実施の形態に限定され
ることはない。上記第1乃至第5の実施の形態におい
て、U−MOSFETからなる半導体装置とその製造方
法について説明したが、例えばU−IGBTのように、
部分的にU−MOFETと同様の構造を有する半導体装
置とその製造方法に本発明が適用されることはいうまで
もない。The present invention is not limited to the above embodiment. In the first to fifth embodiments, the semiconductor device including the U-MOSFET and the method of manufacturing the same have been described. For example, like the U-IGBT,
It goes without saying that the present invention is applied to a semiconductor device partially having a structure similar to that of a U-MOFET and a manufacturing method thereof.
【0050】このときU−MOSFETとして問題にさ
れたチャネルリークは、U−IGBTのラッチアップに
関わるので、前記チャネルリークの低減はU−IGBT
のラッチアップの抑制に役立つ。このほか一般にトレン
チゲートを有する半導体装置とその製造方法に対して本
発明を適用することができる。At this time, the channel leak which is a problem as the U-MOSFET is related to the latch-up of the U-IGBT.
This helps to suppress latch-up. In addition, the present invention can be generally applied to a semiconductor device having a trench gate and a manufacturing method thereof.
【0051】また増速酸化作用を有する不純物として
P、As、Sb、Bを用いたが、これらを混合すること
によっても同様の効果を得ることができる。本発明の半
導体装置の形成に必要な第1導電型及び第2導電型の各
層の形成には、不純物拡散の他イオン注入法や選択エピ
タキシャル法等を用いることができる。また以上説明し
た半導体装置の構造において、シリコン中の各構成領域
の導電型を反転することにより、本発明の特徴を具備す
るpチャネルU−MOSFETが形成されることはいう
までもない。その他、本発明の要旨を逸脱しない範囲
で、種々に変形して実施することができる。Although P, As, Sb, and B are used as impurities having a speed-up oxidizing effect, the same effect can be obtained by mixing these. The first conductivity type and the second conductivity type layers required for forming the semiconductor device of the present invention can be formed by ion implantation, selective epitaxial growth, or the like in addition to impurity diffusion. In the structure of the semiconductor device described above, it is needless to say that a p-channel U-MOSFET having the features of the present invention is formed by inverting the conductivity type of each constituent region in silicon. In addition, various modifications can be made without departing from the scope of the present invention.
【0052】[0052]
【発明の効果】上述したように本発明のトレンチゲート
を有する半導体装置とその製造方法によれば、チャネル
リーク特性に何等影響を及ぼすことなく、ゲート・ソー
ス間耐圧を大幅に向上した半導体装置とその製造方法を
得ることが可能になる。As described above, according to the semiconductor device having a trench gate and the method of manufacturing the same of the present invention, a semiconductor device having a greatly improved gate-source withstand voltage without affecting the channel leak characteristics at all. It becomes possible to obtain the manufacturing method.
【図1】本発明の第1の実施の形態に係るトレンチゲー
ト引き出し部の構造を示す図であって、(a)はその平
面図。(b)はそのA−A断面図。FIG. 1 is a diagram showing a structure of a trench gate lead-out portion according to a first embodiment of the present invention, and FIG. (B) is the AA sectional view.
【図2】本発明の半導体装置のゲート・ソース間耐圧を
従来例と対比して示す図。FIG. 2 is a diagram showing a gate-source breakdown voltage of a semiconductor device of the present invention in comparison with a conventional example.
【図3】本発明の半導体装置のチャネルリーク特性を従
来例と対比して示す図。FIG. 3 is a diagram showing channel leak characteristics of a semiconductor device of the present invention in comparison with a conventional example.
【図4】本発明の半導体装置の断面図であって、(a)
は第3の実施の形態に係る半導体装置の断面図。(b)
は第4の実施の形態に係る半導体装置の断面図。FIG. 4 is a cross-sectional view of the semiconductor device of the present invention, in which (a)
9 is a cross-sectional view of the semiconductor device according to the third embodiment. (B)
9 is a sectional view of a semiconductor device according to a fourth embodiment.
【図5】本発明の第5の実施の形態に係る半導体装置の
製造方法を示す工程断面図。FIG. 5 is a process sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment of the present invention.
【図6】本発明の第5の実施の形態に係る半導体装置の
製造方法の続きを示す工程断面図。FIG. 6 is a process cross-sectional view showing a continuation of the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.
【図7】従来のトレンチゲート引き出し部の構造を示す
図であって、(a)はその平面図。(b)はそのB−B
断面図。7A and 7B are views showing a structure of a conventional trench gate lead-out portion, and FIG. 7A is a plan view thereof. (B) is the BB
Sectional view.
1…n+ 基板 2…n- エピタキシャル層 3…pベース層 4…n+ ソース高不純物濃度層 4a…増速酸化用n+ 高不純物濃度層 4b…チャネルストップ用p+ ウエル 4c…増速酸化用p+ 高不純物濃度層 5…トレンチ 6…熱酸化膜 7…埋め込みポリシリコン 8…ポリシリコンゲートパッド 9…コンタクトホール 10…SiO2 拡散マスク 11…SiO2 エッチングマスク 12…CVD SiO2 膜 13…金属配線DESCRIPTION OF SYMBOLS 1 ... n + substrate 2 ... n - epitaxial layer 3 ... p base layer 4 ... n + source high impurity concentration layer 4a ... n + high impurity concentration layer for accelerated oxidation 4b ... p + well for channel stop 4c ... accelerated oxidation P + high impurity concentration layer 5 trench 6 thermal oxide film 7 buried polysilicon 8 polysilicon gate pad 9 contact hole 10 SiO 2 diffusion mask 11 SiO 2 etching mask 12 CVD SiO 2 film 13 Metal wiring
───────────────────────────────────────────────────── フロントページの続き (72)発明者 八幡 重夫 神奈川県川崎市幸区小向東芝町1番地 株 式会社東芝多摩川工場内 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shigeo Yawata 1 Komagi Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Tamagawa Plant
Claims (8)
1層の第1導電型のドレイン層と、 このドレイン層上に積層された第2導電型のベース層
と、 このベース層を貫通し、前記ドレイン層に達するトレン
チと、 ゲートパッドの下部において前記トレンチの開口周辺に
前記ベース層の厚さより浅く形成された増速酸化に役立
つ高不純物濃度層と、 前記トレンチの内部表面を含むシリコン表面を覆う熱酸
化膜とを備え、 前記増速酸化に役立つ高不純物濃度層により、前記トレ
ンチの開口周辺のエッジ部分における前記熱酸化膜の膜
厚が、前記シリコン表面における平面上の膜厚と同等に
されたことを特徴とする半導体装置。A first conductive type drain layer formed on a silicon substrate; a second conductive type base layer laminated on the drain layer; A trench reaching the drain layer, a high impurity concentration layer useful for enhanced oxidation formed below the gate pad around the opening of the trench and smaller than the thickness of the base layer, and covering a silicon surface including an inner surface of the trench A high-impurity-concentration layer serving for the speed-up oxidation, wherein the thickness of the thermal oxide film at an edge portion around the opening of the trench is made equal to the thickness of the silicon surface on a plane. A semiconductor device characterized by the above-mentioned.
は、少なくともP、As、Sb及びBのいずれか1つを
含むことを特徴とする請求項1記載の半導体装置。2. The semiconductor device according to claim 1, wherein the impurity added to the high impurity concentration layer contains at least one of P, As, Sb, and B.
ティングとされたことを特徴とする請求項1記載の半導
体装置。3. The semiconductor device according to claim 1, wherein said high impurity concentration layer is electrically floating.
も前記ゲートパッドの下部において、第2導電型の不純
物が高濃度に添加されたものであることを特徴とする請
求項1記載の半導体装置。4. The semiconductor according to claim 1, wherein the second conductivity type base layer is formed by adding a second conductivity type impurity at a high concentration at least below the gate pad. apparatus.
も前記ゲートパッドの下部において、第2導電型の不純
物が高濃度に添加されたウエル領域を含むことを特徴と
する請求項1記載の半導体装置。5. The semiconductor device according to claim 1, wherein the base layer of the second conductivity type includes a well region to which a second conductivity type impurity is added at a high concentration at least below the gate pad. Semiconductor device.
導電型のドレイン層を形成し、 このドレイン層上に隣接して第2導電型のベース層を形
成し、 このベース層表面の内、少なくともゲートパッドの下部
において、トレンチの開口位置を規定するトレンチパタ
ーン内とその周辺領域に、少なくともP、AS、Sb及
びBのいずれか1つを選択拡散又はイオン注入すること
により、増速酸化に役立つ高不純物濃度層を前記ベース
層の厚さより浅く形成し、 前記高不純物濃度層と前記ベース層とを貫通して前記ド
レイン層に達するトレンチを、前記トレンチパターンに
より形成されたエッチングマスクを用いて異方性エッチ
ングすることにより形成し、 前記トレンチの内部表面を含むシリコン表面を熱酸化す
ることにより、前記トレンチの開口周辺に残された前記
増速酸化に役立つ高不純物濃度層により、前記トレンチ
の開口周辺のエッジ部分における熱酸化膜の膜厚が、前
記シリコン表面における平面上の膜厚と同等になるよう
にされたことを特徴とする半導体装置の製造方法。6. A method according to claim 1, wherein at least one first layer is formed on a silicon substrate.
Forming a drain layer of a conductivity type, forming a base layer of a second conductivity type adjacent to the drain layer, and defining an opening position of the trench at least at a lower portion of a gate pad in a surface of the base layer; By selectively diffusing or ion-implanting at least one of P, AS, Sb and B in the pattern and its peripheral region, a high impurity concentration layer useful for enhanced oxidation is formed shallower than the thickness of the base layer. Forming a trench penetrating the high impurity concentration layer and the base layer and reaching the drain layer by anisotropically etching using an etching mask formed by the trench pattern; A high impurity concentration layer useful for the accelerated oxidation left around the opening of the trench by thermally oxidizing a silicon surface containing A thickness of the thermal oxide film at an edge portion around the opening of the trench is made equal to a thickness on a plane on the silicon surface.
前記第2導電型のベース層で囲まれるようにパターン形
成されたものであることを特徴とする請求項6記載の半
導体装置の製造方法。7. The manufacturing method of a semiconductor device according to claim 6, wherein said high impurity concentration layer is patterned so that the entire periphery thereof is surrounded by said second conductivity type base layer. Method.
とも前記ゲートパッドの下部領域に、第2導電型の不純
物を選択拡散又はイオン注入することにより高不純物濃
度のウエル領域を形成することを特徴とする請求項6記
載の半導体装置の製造方法。8. A well region having a high impurity concentration is formed by selectively diffusing or ion-implanting an impurity of a second conductivity type in at least a region below the gate pad in the base layer of the second conductivity type. 7. The method for manufacturing a semiconductor device according to claim 6, wherein:
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JP07117697A JP3413050B2 (en) | 1997-03-25 | 1997-03-25 | Semiconductor device and manufacturing method thereof |
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JP3413050B2 JP3413050B2 (en) | 2003-06-03 |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000269499A (en) * | 1999-03-19 | 2000-09-29 | Toshiba Corp | Insulated gate type of transistor, and its manufacture |
JP2003282870A (en) * | 2002-03-20 | 2003-10-03 | Fuji Electric Co Ltd | Semiconductor device and its fabricating method |
JP2004140086A (en) * | 2002-10-16 | 2004-05-13 | Toyota Central Res & Dev Lab Inc | Trench gate semiconductor device |
JP2011192822A (en) * | 2010-03-15 | 2011-09-29 | Fuji Electric Co Ltd | Semiconductor device |
JP2015153988A (en) * | 2014-02-18 | 2015-08-24 | 新日本無線株式会社 | semiconductor device |
JP2018085531A (en) * | 2018-01-05 | 2018-05-31 | ローム株式会社 | Semiconductor device |
JP2018098288A (en) * | 2016-12-09 | 2018-06-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
-
1997
- 1997-03-25 JP JP07117697A patent/JP3413050B2/en not_active Expired - Lifetime
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000269499A (en) * | 1999-03-19 | 2000-09-29 | Toshiba Corp | Insulated gate type of transistor, and its manufacture |
JP2003282870A (en) * | 2002-03-20 | 2003-10-03 | Fuji Electric Co Ltd | Semiconductor device and its fabricating method |
JP2004140086A (en) * | 2002-10-16 | 2004-05-13 | Toyota Central Res & Dev Lab Inc | Trench gate semiconductor device |
JP2011192822A (en) * | 2010-03-15 | 2011-09-29 | Fuji Electric Co Ltd | Semiconductor device |
JP2015153988A (en) * | 2014-02-18 | 2015-08-24 | 新日本無線株式会社 | semiconductor device |
JP2018098288A (en) * | 2016-12-09 | 2018-06-21 | ルネサスエレクトロニクス株式会社 | Semiconductor device and method of manufacturing the same |
JP2018085531A (en) * | 2018-01-05 | 2018-05-31 | ローム株式会社 | Semiconductor device |
Also Published As
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