JP3113426B2 - Insulated gate semiconductor device and method of manufacturing the same - Google Patents

Insulated gate semiconductor device and method of manufacturing the same

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Publication number
JP3113426B2
JP3113426B2 JP04318482A JP31848292A JP3113426B2 JP 3113426 B2 JP3113426 B2 JP 3113426B2 JP 04318482 A JP04318482 A JP 04318482A JP 31848292 A JP31848292 A JP 31848292A JP 3113426 B2 JP3113426 B2 JP 3113426B2
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Japan
Prior art keywords
region
film
refractory metal
composite film
gate electrode
Prior art date
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Expired - Fee Related
Application number
JP04318482A
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JPH06163906A (en
Inventor
正 夏目
茂実 岡田
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H01L21/2815—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【産業上の利用分野】本発明は、絶縁ゲート半導体装置
及びその製造方法に係り、特にドレイン領域となる半導
体基板上にゲート電極をマスクとして、チャネル領域と
ソース領域とが二重に拡散された縦型構造のパワーＭＯ
ＳＦＥＴ、又は絶縁ゲートバイポーラトランジスタ（Ｉ
ＧＢＴ）及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same. Power MO with vertical structure
SFET or insulated gate bipolar transistor (I
GBT) and a manufacturing method thereof.

【０００２】[0002]

【従来の技術】図５は、従来の一般的な縦型パワーＭＯ
ＳＦＥＴの断面図である。Ｎ+ 型半導体基板１には、ド
レイン領域となるＮ- 型エピタキシャル層２を有してい
る。ＭＯＳＦＥＴのセル領域部分はＰ+ 型のボディ領域
６及びＰ型のチャネル領域３にＮ+ 型のソース領域５が
ゲート電極８をマスクとして二重に拡散により形成され
ている。2. Description of the Related Art FIG. 5 shows a conventional general vertical power MO.
It is sectional drawing of SFET. The N + type semiconductor substrate 1 has an N − type epitaxial layer 2 serving as a drain region. In the cell region portion of the MOSFET, an N + -type source region 5 is formed in a P + -type body region 6 and a P-type channel region 3 by double diffusion using a gate electrode 8 as a mask.

【０００３】セル領域以外のフィールド領域は、多結晶
シリコン膜からなるゲート電極８が、薄いゲート酸化膜
７を介して半導体基板上に配置されており、又フィール
ド領域のゲート電極８によって各セルのゲート電極が相
互に配線されている。又、アルミからなる金属電極１１
が、各セルのソース領域５及びチャネル領域３と接続さ
れ、フィールド領域では厚い絶縁膜９を介してゲート電
極８上に配置されている。ＭＯＳＦＥＴの１チップに
は、多数のこのようなセルが配列されており、各セルの
チャネル領域及びソース領域は金属電極１１により、ゲ
ートはゲート電極８によりドレイン領域は裏面電極１０
によりそれぞれ相互に接続配線されている。In a field region other than the cell region, a gate electrode 8 made of a polycrystalline silicon film is disposed on a semiconductor substrate via a thin gate oxide film 7, and each cell is formed by a gate electrode 8 in the field region. Gate electrodes are interconnected. Also, a metal electrode 11 made of aluminum
Are connected to the source region 5 and the channel region 3 of each cell, and are arranged on the gate electrode 8 via the thick insulating film 9 in the field region. A large number of such cells are arranged in one chip of the MOSFET, and the channel region and the source region of each cell are formed by the metal electrode 11, the gate is formed by the gate electrode 8, and the drain region is formed by the back surface electrode 10.
Are connected to each other.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、係る縦
型パワーＭＯＳＦＥＴは、ゲート電極８がフィールド領
域において薄いゲート酸化膜７を介して半導体基板のド
レイン領域２に対面しているため、ゲートとドレイン端
子間の浮遊容量が大きくなり、高速化、高周波化の１つ
のネックとなっていた。However, in such a vertical power MOSFET, since the gate electrode 8 faces the drain region 2 of the semiconductor substrate via the thin gate oxide film 7 in the field region, the gate and the drain terminal are not connected. The stray capacitance between them has increased, which has been one of the bottlenecks in increasing the speed and increasing the frequency.

【０００５】係る縦型パワーＭＯＳＦＥＴの浮遊容量の
低減を図るために、図６に示すような構造が考えられ
る。これは、フィールド領域において、ゲート電極８の
直下を厚い酸化膜１７として半導体基板上に大きな面積
を占めるフィールド領域のゲートとドレイン間の容量を
低減しようとするものである。In order to reduce the stray capacitance of such a vertical power MOSFET, a structure as shown in FIG. 6 can be considered. This is to reduce the capacitance between the gate and the drain in the field region which occupies a large area on the semiconductor substrate by forming a thick oxide film 17 immediately below the gate electrode 8 in the field region.

【０００６】図７は、同様にフィールド領域のゲート電
極８とドレイン領域２間の浮遊容量を低減するために、
提案された構造であり、半導体基板上で大きな面積を占
めるフィールド領域のゲート電極８を必要な各セル部分
の相互接続部分のみを残し、他を取り除くことにより、
浮遊容量の低減を図るものである。FIG. 7 is a view similar to FIG. 1 for reducing the stray capacitance between the gate electrode 8 and the drain region 2 in the field region.
In the proposed structure, the gate electrode 8 in the field region occupying a large area on the semiconductor substrate is removed by leaving only the necessary interconnect portion of each cell portion and removing the others.
The purpose is to reduce stray capacitance.

【０００７】しかしながら、特に低圧系の縦型パワーＭ
ＯＳＦＥＴにおいては、低オン抵抗化、高速化、高周波
化のためパターンの微細化が進み、フォトリソグラフィ
によるマスク合わせを必要とする上述の図６、図７に説
明した方法では限界がきていた。例えば、６０Ｖクラス
の低圧パワーＭＯＳＦＥＴでは、セル領域におけるゲー
トのチャネル長を１〜２μ、セル間のゲート電極幅を５
〜８μに形成しようとすると、マスク合わせ精度の限界
から、上述の方法ではゲート電極の加工が困難であり、
実施が難しいものとなってしまう。However, in particular, the vertical power M
In the OSFET, pattern miniaturization has progressed for low on-resistance, high speed, and high frequency, and the method described in FIGS. 6 and 7 which requires mask alignment by photolithography has reached its limit. For example, in a low-voltage power MOSFET of a 60 V class, a channel length of a gate in a cell region is 1 to 2 μm, and a gate electrode width between cells is 5 μm.
If it is attempted to form the gate electrode with a thickness of about 8 μm, it is difficult to process the gate electrode by the above-described method due to the limitation of mask alignment accuracy.
It will be difficult to implement.

【０００８】本発明は、係る従来技術の問題点に鑑み、
高速化、高周波化、低オン抵抗化に好適なパワーＭＯＳ
ＦＥＴ（ＩＧＢＴ）及びその製造方法を提供することを
目的とする。The present invention has been made in view of the above-mentioned problems of the prior art,
Power MOS suitable for high speed, high frequency, low on-resistance
An object of the present invention is to provide an FET (IGBT) and a method for manufacturing the same.

【０００９】[0009]

【課題を解決するための手段】本発明に係る絶縁ゲート
半導体装置は、フィールド領域に配置される厚い酸化膜
と多結晶シリコン膜と高融点金属のシリサイド層からな
る複合膜と、該複合膜に隣接して設けられた前記高融点
金属のシリサイド層に接続された高融点金属のサイドウ
ォールと、該サイドウォール及び該複合膜をマスクとし
て二重に拡散により配置されたチャネル領域とソース領
域とを備えたことを特徴とするものである。According to the present invention, there is provided an insulated gate semiconductor device comprising a composite film comprising a thick oxide film, a polycrystalline silicon film and a refractory metal silicide layer disposed in a field region; A side wall of the high melting point metal connected to the silicide layer of the high melting point metal provided adjacently, and a channel region and a source region arranged by doubly diffusion using the side wall and the composite film as a mask. It is characterized by having.

【００１０】又、その製造方法は、半導体基板上に厚い
酸化膜と多結晶シリコン層と高融点金属のシリサイド層
かならなる複合膜を形成する工程と、該複合膜のフィー
ルド領域となる部分を残しセル領域を開口する工程と、
薄い酸化膜を前記開口されたセル領域に被着して前記複
合膜に隣接して高融点金属のサイドウォールを形成する
工程と、該高融点金属のサイドウォールをマスクとして
チャネル領域及びソース領域を二重に拡散により形成す
る工程とからなることを特徴とするものである。Further, the manufacturing method includes a step of forming a composite film consisting of a thick oxide film, a polycrystalline silicon layer and a refractory metal silicide layer on a semiconductor substrate, and a step of forming a field region of the composite film as a field region. Opening the remaining cell area;
Applying a thin oxide film to the open cell region to form a refractory metal sidewall adjacent to the composite film; and forming the channel region and the source region using the refractory metal sidewall as a mask. And a step of doubly forming by diffusion.

【００１１】[0011]

【作用】フィールド領域に配置される厚い酸化膜と多結
晶シリコン膜と高融点金属のシリサイド層を備えた複合
膜に隣接して設けられた高融点金属のサイドウォールに
よって、セル領域のゲート電極部分をセルフアラインで
精度よく形成することができる。そして、高融点金属の
サイドウォールはフィールド領域の厚い酸化膜上に形成
された高融点金属のシリサイド層に接続されていること
から、フィールド領域のゲート電極直下の酸化膜の膜厚
を厚くすることができる。従って、ゲートとドレイン間
の浮遊容量を低減し、且つゲート電極の配線抵抗をシリ
サイド層により低減することができる。それ故、ＭＯＳ
ＦＥＴの実質的な作動部分となるゲート電極を短く、且
つ精度よく形成することができ、低オン抵抗の、浮遊容
量の低減された縦型絶縁ゲート半導体装置が実現され
る。The gate electrode portion of the cell region is formed by a refractory metal sidewall provided adjacent to a composite film including a thick oxide film, a polycrystalline silicon film, and a refractory metal silicide layer disposed in a field region. Can be accurately formed by self-alignment. Since the refractory metal sidewall is connected to the refractory metal silicide layer formed on the thick oxide film in the field region, the thickness of the oxide film immediately below the gate electrode in the field region should be increased. Can be. Therefore, the floating capacitance between the gate and the drain can be reduced, and the wiring resistance of the gate electrode can be reduced by the silicide layer. Therefore, MOS
A gate electrode, which is a substantial operating part of the FET, can be formed short and accurately, and a vertical insulated gate semiconductor device with low on-resistance and reduced stray capacitance is realized.

【００１２】[0012]

【実施例】以下、本発明の一実施例を添付図面を参照し
ながら説明する。An embodiment of the present invention will be described below with reference to the accompanying drawings.

【００１３】図１は、本発明の一実施例の縦型パワーＭ
ＯＳＦＥＴの断面図である。Ｎ+ 型シリコン半導体基板
１は、ドレイン領域２となるＮ- 型エピタキシャル層を
備え、半導体基板１の裏面電極１０はＭＯＳＦＥＴのド
レイン電極となる。フィールド領域には、半導体基板上
に厚い酸化膜１５と、多結晶シリコン膜８と、タングス
テン等の高融点金属のシリサイド層１２とからなる複合
膜が配置される。シリサイド層１２は、複合膜に隣接し
て設けられたタングステン等の高融点金属のサイドウォ
ール１３に電気的に接続されている。複合膜の上には、
厚い絶縁膜９を介してソース電極となる金属電極１１が
被着されている。FIG. 1 shows a vertical power M according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of an OSFET. The N + type silicon semiconductor substrate 1 includes an N − type epitaxial layer serving as a drain region 2, and the back surface electrode 10 of the semiconductor substrate 1 serves as a drain electrode of a MOSFET. In the field region, a composite film including a thick oxide film 15, a polycrystalline silicon film 8, and a silicide layer 12 of a refractory metal such as tungsten is arranged on a semiconductor substrate. The silicide layer 12 is electrically connected to a side wall 13 of a refractory metal such as tungsten provided adjacent to the composite film. On the composite membrane,
A metal electrode 11 serving as a source electrode is attached via a thick insulating film 9.

【００１４】セル領域には、セル領域の実質的なゲート
電極の作動部分となる高融点金属サイドウォール１３が
フィールド領域の複合膜１５，８，１２に隣接して配置
される。Ｐ型のチャネル領域３及びＮ+ 型のソース領域
５は高融点金属サイドウォール１３及びフィールド領域
の複合膜をマスクとして二重に拡散により形成されたも
のである。ボディ領域６は、チャネル領域３と同様なＰ
型の高濃度領域であり、複合膜のセル領域部分の開口に
先立って拡散により形成される。ボディ領域６はチャネ
ル領域３の抵抗を低減することにより、アバランシェ
（ラッチアップ）耐量を増大するためのものである。In the cell region, a refractory metal sidewall 13 which is a substantial operating portion of the gate electrode in the cell region is arranged adjacent to the composite films 15, 8, and 12 in the field region. The P-type channel region 3 and the N + -type source region 5 are formed by double diffusion using the refractory metal sidewall 13 and the composite film of the field region as a mask. The body region 6 has the same P
This is a high-concentration region of the mold, and is formed by diffusion prior to the opening of the cell region of the composite film. The body region 6 is for reducing the resistance of the channel region 3 to increase the avalanche (latch-up) resistance.

【００１５】係る構造のＭＯＳＦＥＴは、高融点金属サ
イドウォール１３がセル部分のゲート電極としての役割
を果たし、直下のチャネル領域３を反転させることによ
り、ドレイン領域２からソース領域５に流れる電流を制
御する。このように、実質的なゲート電極となる高融点
金属サイドウォール１３は、厚い酸化膜等からなる複合
膜１５，１２，８に隣接して設けられるため、１〜２ミ
クロン程度の短いゲート電極部分を精度よく形成するこ
とができる。In the MOSFET having such a structure, the refractory metal sidewall 13 functions as a gate electrode in the cell portion, and the current flowing from the drain region 2 to the source region 5 is controlled by inverting the channel region 3 immediately below. I do. As described above, since the refractory metal sidewall 13 serving as a substantial gate electrode is provided adjacent to the composite films 15, 12, and 8 made of a thick oxide film or the like, the gate electrode portion having a short length of about 1 to 2 microns is provided. Can be accurately formed.

【００１６】そして、フィールド領域においては、ゲー
ト電極の配線部分８は厚い酸化膜１５上の多結晶シリコ
ン膜８及びシリサイド層１２によって形成される。それ
故、フィールド領域におけるゲート電極の配線部分は、
浮遊容量を小さく、かつ低い抵抗値にすることができ
る。従って、セルフアラインにより形成された微細な金
属サイドウォール１３によるゲート電極と、低いゲート
とドレイン間の浮遊容量及び低いゲートの配線抵抗によ
り高速、高周波特性の優れた低オン抵抗の縦型パワーＭ
ＯＳＦＥＴが実現される。In the field region, the wiring portion 8 of the gate electrode is formed by the polycrystalline silicon film 8 on the thick oxide film 15 and the silicide layer 12. Therefore, the wiring portion of the gate electrode in the field region is
The stray capacitance can be reduced and the resistance can be reduced. Therefore, the vertical power M with excellent high-speed and high-frequency characteristics is provided by the gate electrode formed by the fine metal sidewall 13 formed by self-alignment, the low floating capacitance between the gate and the drain, and the low wiring resistance of the gate.
An OSFET is implemented.

【００１７】図２乃至図４は、本発明の一実施例のパワ
ーＭＯＳＦＥＴの製造工程の断面図である。以下に、本
ＭＯＳＦＥＴの製造方法について説明する。FIGS. 2 to 4 are cross-sectional views showing the steps of manufacturing a power MOSFET according to one embodiment of the present invention. Hereinafter, a method for manufacturing the MOSFET will be described.

【００１８】まず、上部にドレイン領域２となるＮ- 型
エピタキシャル層を備えたＮ+ 型半導体基板１を準備す
る。次に、Ｐ+ 型のボディ領域６を拡散により形成す
る。そして、半導体基板上に熱酸化による厚い酸化膜１
５と、多結晶シリコン膜８及びタングステンシリサイド
層７からなる複合膜を順次形成する。そして、予め拡散
により形成されたボディ領域６に対してセル領域パター
ンのマスク合わせを行い、エッチングによりシリサイド
層７及び多結晶シリコン膜８に開口部を設ける。図２
は、この工程の段階を示す。First, an N + type semiconductor substrate 1 having an N − type epitaxial layer to be a drain region 2 thereon is prepared. Next, a P + type body region 6 is formed by diffusion. Then, a thick oxide film 1 is formed on the semiconductor substrate by thermal oxidation.
5 and a composite film composed of a polycrystalline silicon film 8 and a tungsten silicide layer 7 are sequentially formed. Then, masking of the cell region pattern is performed on the body region 6 formed by diffusion in advance, and openings are provided in the silicide layer 7 and the polycrystalline silicon film 8 by etching. FIG.
Indicates the stage of this process.

【００１９】次に、フィールド領域となる部分のシリサ
イド層７及び多結晶シリコン膜８をマスクとして、セル
領域となる部分の厚い酸化膜１５をエッチングする。そ
して、開口されたセル領域部分にゲート酸化膜７となる
薄い酸化膜をシリコン半導体基板上に成長させる。そし
て、タングステン等の高融点金属膜１６を全面にデポジ
ションする。図３は、この工程の段階を示す。Next, using the silicide layer 7 and the polycrystalline silicon film 8 in the portion to be the field region as a mask, the thick oxide film 15 in the portion to be the cell region is etched. Then, a thin oxide film serving as the gate oxide film 7 is grown on the silicon semiconductor substrate in the opened cell region. Then, a refractory metal film 16 such as tungsten is deposited on the entire surface. FIG. 3 shows the stages of this process.

【００２０】そして、この高融点金属膜１６を等方性エ
ッチングによりエッチバックし、シリコン半導体基板上
のゲート酸化膜７が露出する段階までエッチングするこ
とにより、高融点金属サイドウォール１３が形成され
る。このように、高融点金属サイドウォール１３は、フ
ィールド領域の厚い酸化膜１５等からなる複合膜に隣接
してセルフアラインにより形成される。尚、高融点金属
サイドウォール１３は、高融点金属の選択ＣＶＤによっ
て形成してもよい。そして、高融点金属サイドウォール
はゲート電極の配線部分となる複合膜のシリサイド層１
２と接触し電気的に接続される。The refractory metal film 16 is etched back by isotropic etching until the gate oxide film 7 on the silicon semiconductor substrate is exposed, thereby forming the refractory metal sidewall 13. . As described above, the refractory metal sidewall 13 is formed by self-alignment adjacent to the composite film including the thick oxide film 15 in the field region. The refractory metal sidewall 13 may be formed by selective CVD of a refractory metal. Then, the refractory metal sidewall is a silicide layer 1 of a composite film serving as a wiring portion of a gate electrode.
2 and is electrically connected.

【００２１】高融点金属サイドウォール１３及びフィー
ルド領域の複合膜１２，８，１５をマスクとして、Ｐ型
不純物をイオン注入しドライブインすることによって、
チャネル領域３を形成する。次に、マスク合わせにより
ソース領域を形成するためのレジストマスク１８を形成
する。このレジストマスク１８及び高融点金属サイドウ
ォール１３をマスクとして、高濃度のＮ型不純物をイオ
ン注入する。そして、ホトレジスト膜１７を除去して、
熱処理によりＮ+ 型のソース領域５を形成する。従っ
て、ゲート電極の役割を果たす高融点金属サイドウォー
ル１３をマスクとして、Ｐ型のチャネル領域３及びＮ+
型のソース領域５とが二重にセルフアラインにより形成
される。図４はこの工程の段階を示す。Using the refractory metal sidewall 13 and the composite films 12, 8, and 15 in the field region as a mask, a P-type impurity is ion-implanted and drive-in is performed.
A channel region 3 is formed. Next, a resist mask 18 for forming a source region is formed by mask alignment. Using the resist mask 18 and the refractory metal sidewall 13 as a mask, high-concentration N-type impurities are ion-implanted. Then, the photoresist film 17 is removed,
An N + type source region 5 is formed by heat treatment. Accordingly, the P-type channel region 3 and the N +
The mold source region 5 is double formed by self-alignment. FIG. 4 illustrates the steps in this process.

【００２２】以降の製造工程は、従来の縦型パワーＭＯ
ＳＦＥＴと同様である。先ず、セル部分の露出している
薄い酸化膜を除去して、シリコン半導体基板を露出さ
せ、全面に金属電極となるアルミ膜を蒸着等により被着
する。そして金属電極のパターンによってマスク合わ
せ、エッチングの工程を経て図１に示す金属電極１１を
備えた縦型パワーＭＯＳＦＥＴが完成する。Subsequent manufacturing steps are performed using a conventional vertical power MO.
Same as SFET. First, the exposed thin oxide film in the cell portion is removed to expose the silicon semiconductor substrate, and an aluminum film serving as a metal electrode is deposited on the entire surface by vapor deposition or the like. Then, a vertical power MOSFET including the metal electrode 11 shown in FIG. 1 is completed through a masking process and an etching process according to the pattern of the metal electrode.

【００２３】なお、以上の説明はパワーＭＯＳＦＥＴに
ついてのものであるが、Ｐ+ 型半導体基板１を用いるこ
とによって、絶縁ゲートバイポーラトランジスタ（ＩＧ
ＢＴ）とすることができる。このような構造のＩＧＢＴ
においても、微細構造のゲート電極で、ゲート電極の配
線部分の浮遊容量が少なく、かつ配線抵抗を小さく製造
することができる。Although the above description has been made with respect to the power MOSFET, the use of the P + type semiconductor substrate 1 allows the insulated gate bipolar transistor (IG) to be used.
BT). IGBT with such a structure
In this case, a gate electrode having a fine structure can be manufactured with a small floating capacitance at a wiring portion of the gate electrode and a low wiring resistance.

【００２４】[0024]

【発明の効果】以上に説明したように、本発明の半導体
装置は、フィールド領域に配置される厚い酸化膜と多結
晶シリコン膜と高融点金属のシリサイド層からなる複合
膜と、該複合膜に隣接してセルフアラインにより設けら
れた高融点金属のサイドウォールと、該サイドウォール
をマスクとしてセルフアラインにより形成されるチャネ
ル領域とソース領域とを備えていることを特徴とする。
従って、高融点金属のサイドウォールがフィールド領域
に配置される複合膜に隣接してセルフアラインにより形
成されることから、ＭＯＳＦＥＴの実質的な作動部分と
なるゲート電極を短く、且つ精度よく形成することがで
きる。As described above, the semiconductor device of the present invention comprises a composite film composed of a thick oxide film, a polycrystalline silicon film and a refractory metal silicide layer disposed in a field region; It is characterized by comprising a refractory metal sidewall provided adjacently by self-alignment, and a channel region and a source region formed by self-alignment using the sidewall as a mask.
Therefore, since the refractory metal sidewall is formed by self-alignment adjacent to the composite film disposed in the field region, the gate electrode, which is a substantial operating portion of the MOSFET, is formed short and accurately. Can be.

【００２５】又、ゲート電極の役割を果たす高融点金属
のサイドウォールは、配線部分となるフィールド領域の
複合膜のシリサイド層と接続されている。そして、複合
膜のシリサイド層は厚い酸化膜上に設けられているた
め、ゲート／ドレイン間の浮遊容量を低減することがで
きる。又、ゲート電極の配線部分となるフィールド領域
の厚い酸化膜上には、多結晶シリコン膜とシリサイド層
を備えているため、ゲート電極の配線部分の抵抗を低減
することができる。それ故、本発明によれば、セルフア
ラインによる短いゲート電極、低いゲート電極の配線部
分の浮遊容量、低いゲート電極の配線部分の抵抗が実現
され、高速、高周波特性の優れた、低オン抵抗のパワー
ＭＯＳＦＥＴ（ＩＧＢＴ）が良好な製造歩留で実現され
る。The sidewall of the refractory metal serving as the gate electrode is connected to the silicide layer of the composite film in the field region serving as a wiring portion. Since the silicide layer of the composite film is provided on the thick oxide film, the floating capacitance between the gate and the drain can be reduced. Further, since the polycrystalline silicon film and the silicide layer are provided on the thick oxide film in the field region serving as the wiring portion of the gate electrode, the resistance of the wiring portion of the gate electrode can be reduced. Therefore, according to the present invention, a short gate electrode by self-alignment, a stray capacitance of a wiring portion of a low gate electrode, and a resistance of a wiring portion of a low gate electrode are realized. A power MOSFET (IGBT) is realized with a good production yield.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の一実施例の絶縁ゲート半導体装置の断
面図。FIG. 1 is a sectional view of an insulated gate semiconductor device according to one embodiment of the present invention.

【図２】本発明の一実施例の絶縁ゲート半導体装置の製
造方法を説明する断面図。FIG. 2 is a cross-sectional view illustrating a method of manufacturing an insulated gate semiconductor device according to one embodiment of the present invention.

【図３】本発明の一実施例の絶縁ゲート半導体装置の製
造方法を説明する断面図。FIG. 3 is a sectional view illustrating the method of manufacturing the insulated gate semiconductor device according to one embodiment of the present invention.

【図４】本発明の一実施例の絶縁ゲート半導体装置の製
造方法を説明する断面図。FIG. 4 is a cross-sectional view illustrating the method of manufacturing the insulated gate semiconductor device according to one embodiment of the present invention.

【図５】従来の絶縁ゲート半導体装置の断面図。FIG. 5 is a cross-sectional view of a conventional insulated gate semiconductor device.

【図６】従来の絶縁ゲート半導体装置の断面図。FIG. 6 is a cross-sectional view of a conventional insulated gate semiconductor device.

【図７】従来の絶縁ゲート半導体装置の断面図。FIG. 7 is a cross-sectional view of a conventional insulated gate semiconductor device.

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 29/78 H01L 21/336 ──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. 7 , DB name) H01L 29/78 H01L 21/336

Claims (2)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 フィールド領域に配置される厚い酸化膜
と多結晶シリコン膜と高融点金属のシリサイド層からな
る複合膜と、該複合膜に隣接して設けられた前記高融点
金属のシリサイド層に接続された高融点金属のサイドウ
ォールと、該サイドウォール及び該複合膜をマスクとし
て二重に拡散により配置されたチャネル領域とソース領
域とを備えたことを特徴とする絶縁ゲート半導体装置。1. A composite film comprising a thick oxide film, a polycrystalline silicon film and a refractory metal silicide layer disposed in a field region, and a refractory metal silicide layer provided adjacent to the composite film. An insulated gate semiconductor device, comprising: a refractory metal side wall connected thereto; and a channel region and a source region which are arranged by diffusion using the side wall and the composite film as a mask. 【請求項２】 半導体基板上に厚い酸化膜と多結晶シリ
コン膜と高融点金属のシリサイド層かならなる複合膜を
形成する工程と、該複合膜のフィールド領域となる部分
を残しセル領域を開口する工程と、薄い酸化膜を前記開
口されたセル領域に被着して前記複合膜に隣接して高融
点金属のサイドウォールを形成する工程と、該高融点金
属のサイドウォールをマスクとしてチャネル領域及びソ
ース領域を二重に拡散により形成する工程とからなるこ
とを特徴とする絶縁ゲート半導体装置の製造方法。2. A step of forming a composite film composed of a thick oxide film, a polycrystalline silicon film and a silicide layer of a high melting point metal on a semiconductor substrate, and opening a cell region while leaving a portion of the composite film to be a field region. Applying a thin oxide film to the open cell region to form a sidewall of a high melting point metal adjacent to the composite film; and forming a channel region using the high melting point metal sidewall as a mask. And a step of forming a source region by double diffusion.
JP04318482A 1992-11-27 1992-11-27 Insulated gate semiconductor device and method of manufacturing the same Expired - Fee Related JP3113426B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP04318482A JP3113426B2 (en) 1992-11-27 1992-11-27 Insulated gate semiconductor device and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP04318482A JP3113426B2 (en) 1992-11-27 1992-11-27 Insulated gate semiconductor device and method of manufacturing the same

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JPH06163906A JPH06163906A (en) 1994-06-10
JP3113426B2 true JP3113426B2 (en) 2000-11-27

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000051294A (en) * 1999-01-20 2000-08-16 김덕중 DMOS field effect transistor with improved electrical characteristics and fabricating method thereof
US6936527B1 (en) 2000-12-19 2005-08-30 Xilinx, Inc. Low voltage non-volatile memory cell
US6496416B1 (en) 2000-12-19 2002-12-17 Xilinx, Inc. Low voltage non-volatile memory cell
US7410851B2 (en) 2001-07-05 2008-08-12 International Rectifier Corporation Low voltage superjunction MOSFET
US6639276B2 (en) * 2001-07-05 2003-10-28 International Rectifier Corporation Power MOSFET with ultra-deep base and reduced on resistance
US6803317B2 (en) * 2002-08-16 2004-10-12 Semiconductor Components Industries, L.L.C. Method of making a vertical gate semiconductor device
US7045845B2 (en) * 2002-08-16 2006-05-16 Semiconductor Components Industries, L.L.C. Self-aligned vertical gate semiconductor device
US6930920B1 (en) 2002-10-29 2005-08-16 Xilinx, Inc. Low voltage non-volatile memory cell
US20130154017A1 (en) * 2011-12-14 2013-06-20 Microchip Technology Incorporated Self-Aligned Gate Structure for Field Effect Transistor

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