JPS592432A - Analog-digital converter for video signal - Google Patents
Analog-digital converter for video signalInfo
- Publication number
- JPS592432A JPS592432A JP10971082A JP10971082A JPS592432A JP S592432 A JPS592432 A JP S592432A JP 10971082 A JP10971082 A JP 10971082A JP 10971082 A JP10971082 A JP 10971082A JP S592432 A JPS592432 A JP S592432A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- bias voltage
- comparator
- comparators
- converter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/129—Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling ; Out-of-range indication
- H03M1/1295—Clamping, i.e. adjusting the DC level of the input signal to a predetermined value
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
本発明はアナログ−デジタル変換器（以下ＶＤ変換器と
いう）に係シ、特にビデオ信号を扱うに好適なＡ１１）
変換器に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog-to-digital converter (hereinafter referred to as a VD converter), and is particularly suitable for handling video signals (A11).
Regarding converters.
一般に並列形ルの変換器は第１図に示すように基準電圧
を与える電圧源１１分圧抵抗２．比較器３、エンコーデ
ィングのロジック４とから構成される。例えば８ビツト
のデジタル信号への変換１ｃＶｉ２５５個の比較器と基
準電圧を２５５等分する分圧抵抗２とを必要とする。Ｖ
Ｄ変換器へのアナログ入力信号条幅は比較器３への基準
電圧の大きさから定められている。従来のルの変換器は
アナログ入力信号として接地電位から正極性のある値ま
で（例えばＤ〜１０ポルト）、または負極性のある値か
ら正極性のある値まで（例えば−５〜＋５ボルト）を扱
かっている。また比較器は第２図に示すような差動増幅
器で構成されている。したがって入力端子５へ人力され
るアナログ信号の入力値が接地電位または負極性の値で
正常に動作するためには、端子６へは正極性の電源、端
子７へは入力信号値よυ低い負極性の電源を接続しなけ
ればならない。このためルの変換器用として＋１０ボル
トおよび一１０ボルトと２つの電源を必要とする。一般
にテレビ受信機、ビデオテープレコーダなどビデオ信号
を扱う民生機器は電圧が＋１２ボルト程度の一つの電源
で動作しているので、従来のルω変換器を使用するには
負極性の電源を追加しなければならず、不経済となるば
かシか機器内に占める容積も大きく小形化の障害となる
。In general, a parallel converter has a voltage source 11 that provides a reference voltage, a voltage dividing resistor 2, and a voltage dividing resistor 2, as shown in FIG. It consists of a comparator 3 and an encoding logic 4. For example, conversion to an 8-bit digital signal requires 1cVi255 comparators and a voltage dividing resistor 2 that divides the reference voltage into 255 equal parts. V
The width of the analog input signal to the D converter is determined from the magnitude of the reference voltage to the comparator 3. Conventional converters accept analog input signals from ground potential to some positive value (e.g. D to 10 volts) or from some negative polarity to some positive value (e.g. -5 to +5 volts). It's being handled. Further, the comparator is constituted by a differential amplifier as shown in FIG. Therefore, in order for the input value of the analog signal input to input terminal 5 to operate normally with a ground potential or a value of negative polarity, terminal 6 must be connected to a positive polarity power source, and terminal 7 must be connected to a negative polarity that is υ lower than the input signal value. must be connected to a power source. This requires two power supplies, one for +10 volts and one for -10 volts. Generally, consumer equipment that handles video signals, such as television receivers and video tape recorders, operates on a single power supply with a voltage of around +12 volts, so to use a conventional Leω converter, you need to add a negative polarity power supply. This is not only uneconomical, but also occupies a large volume within the device, which becomes an obstacle to downsizing.
本発明の目的は一つの電源で動作する比較器を備えたビ
デオ信号用のＡｌ１）変換器を提供することにある。The object of the invention is to provide an Al1) converter for video signals with a comparator that operates from one power supply.
本発明では、入力信号に負極性の値を含んでいても比較
器が一つの電源で正常に動作をするようにするため、入
力ビデオ信号をルの変換器内のバイアス電圧にクランプ
し、そのバイアス電圧を重畳した基準電圧とクランプさ
れた入力信号を比較器の入力とする。In the present invention, in order to allow the comparator to operate normally with a single power supply even if the input signal contains a negative polarity value, the input video signal is clamped to the bias voltage in the converter. The reference voltage on which the bias voltage is superimposed and the clamped input signal are input to the comparator.
以下、本発明の一実施例を第３図によシ説明する。第３
図において、第１図と同じものには同じ符号を付しであ
る。８はバイアス電圧を与える電圧源、９はクランプ用
ス・イッチ、１０はクランプ用コンデンサを示す。基準
電圧源１の基準電圧を分圧用抵抗２で分圧し、それらに
バイアス電圧源８の電圧を重畳して、比較器への基チ９
とクランプ用コンデンサ１０によシ入カビデオ信号の同
期部分をバイアス電圧源８０レベルにクランプする。そ
の動作は第４図に示すようなビデオ信号が入力端子５へ
印加されると、その信号の同期部分の時刻（第４図のα
）の間だけスイッチ９を閉じてコンデンサ１０をバイア
ス電圧源８で充電する。その結果比較器３へはバイアス
電圧源８の電圧でクランプされたビデオ入力信号と、バ
イアス電圧源８の電圧が重畳された基準電圧とが入力さ
れる。バイアス電圧は両入力に対して同相的に動作する
ので、比較器の比較動作に対しては影響せず、比較器に
バイアス電圧を与えている。したがって第２図に示す方
式の比較器は端子７を接地、端子６へ正極性の一つの電
源を接続することによって正常に比較動作を行なえる。An embodiment of the present invention will be described below with reference to FIG. Third
In the figure, the same parts as in FIG. 1 are given the same reference numerals. Reference numeral 8 indicates a voltage source for applying a bias voltage, 9 indicates a clamp switch, and 10 indicates a clamp capacitor. The reference voltage of the reference voltage source 1 is divided by the voltage dividing resistor 2, the voltage of the bias voltage source 8 is superimposed on them, and the base voltage 9 to the comparator is
The synchronous portion of the input video signal is clamped to the bias voltage source 80 level by the clamping capacitor 10. Its operation is such that when a video signal as shown in Fig. 4 is applied to the input terminal 5, the time of the synchronous part of the signal (α in Fig. 4)
), the switch 9 is closed and the capacitor 10 is charged by the bias voltage source 8. As a result, the video input signal clamped by the voltage of the bias voltage source 8 and the reference voltage on which the voltage of the bias voltage source 8 is superimposed are input to the comparator 3 . Since the bias voltage operates in-phase with respect to both inputs, it does not affect the comparison operation of the comparator, and provides the bias voltage to the comparator. Therefore, the comparator of the type shown in FIG. 2 can perform a normal comparison operation by grounding the terminal 7 and connecting one power source of positive polarity to the terminal 6.
本実施例に示すように入力ビデオ信号の同期部分をバイ
アス電圧でクランプし、また基準電圧に同じバイアス電
圧を重畳することによシ、＆ω変換器の比較器を一つの
電源で動作させることが可能となシ、従来の欠点である
不経済性と小形化への障害を除去できる。As shown in this example, by clamping the synchronous part of the input video signal with a bias voltage and superimposing the same bias voltage on the reference voltage, it is possible to operate the comparator of the &ω converter with a single power supply. This makes it possible to eliminate the disadvantages of the conventional technology, such as uneconomical costs and obstacles to miniaturization.
また第５図に本発明の他の実施例を示す。第５図におい
て第４図の実施例と同じものには同じ符号を付しである
。１１はクランプスイッチ用トランジスタ、１２け基準
電圧用ツェナーダイオード、１５はコンデンサ１ｏの電
荷を長時間保持させるためのバッファ用トランジスタ、
１６けバイアス電圧を定電圧化するためのバッファ用ト
ランジスタ、１７はツェナーダイオード１２による基準
電圧をさらに定電圧化するためのバッファ用トランジス
タ、１４．１５は入力ビデオ信号のバッファトランジス
タ１３による直流シフト量を補償するダイオードを示し
である。Further, FIG. 5 shows another embodiment of the present invention. In FIG. 5, the same parts as in the embodiment of FIG. 4 are given the same reference numerals. 11 is a clamp switch transistor, 12 is a reference voltage Zener diode, 15 is a buffer transistor for holding the charge of the capacitor 1o for a long time,
16 is a buffer transistor for making the bias voltage a constant voltage, 17 is a buffer transistor for further making the reference voltage by the Zener diode 12 a constant voltage, 14.15 is a DC shift amount of the input video signal by the buffer transistor 13 It shows a diode to compensate for.
ツェナダイオード１２のアノード（第５図のＡ点）は抵
抗を通して接地し、カソード（第５図のＢ点）は抵抗を
通して電源に接続しである。The anode (point A in FIG. 5) of the Zener diode 12 is grounded through a resistor, and the cathode (point B in FIG. 5) is connected to the power supply through a resistor.
そして点Ａにバイアス電圧を点Ｂにバイアス電圧を重畳
した基準電圧を発生している。それぞれの電圧はバッフ
ァトランジスタ１６，１７を介してそれぞれのトランジ
スタ４６．１７のエミッタ電位となっている。一方クラ
ンプ用コンデンサはスイッチトランジスタ１１を介して
トランジスタ１６のエミッタへ接続されている。したが
ってビデオ信号の同期部の間にスイッチトランジスタ１
１を導通させると、トランジスタ１５０ペース電位はト
ランジスタ１６のエミッタ鑞付にクランプされる。この
電位は各比較器６（８ピツトの場合２５５個）へ共通に
入力されるので、コンデンサから比較器へ流れる入力！
、流が多くなシ、クランプ電圧が変化する。それを防止
するためバッフ７トランジスタ１３を介して各比較器３
へ入力しである。その結果バッファトランジスタ１５の
入力端子のベース電位と出力端子のエミッタ電位に約０
．７ボルトのベース−エミッタ間電圧の降下が生じ、バ
イアス載位トランジスタ１６のエミッタ電位とに差が生
じ不都合となる。そこでバイアス電位を前記トランジス
タ１５のベース・エミッタ間電圧と等しい電圧だけダイ
オード１４によシ降下させである。またバイアス電位の
み降下させたのでは分圧抵抗２０両端にはツェナダイオ
ード１２による基準電圧よシ前記ダイオード送圧だけ大
きい電圧が加わるので、それを補償するためダイオード
１５を介して分圧抵抗２に基準電圧を印加しである。上
記構成にょシ、各比較器にはバイアス電圧を同相的に与
え、比較動作はツェナーダイオード１２による基準電圧
で行なうことができ、一つの眠源で動かすことができる
。さらに本実施例は半導体集積回路に適したもので、集
積化によりトランジスタ１６と１７およびトランジスタ
１５とダイオード１４．１５のペース−エミッタ間紙圧
を等しく、さらに温度変化にＪ、る値をも等しくできる
。ぞの結沫バイアス送圧によるクランプ電位と基準電圧
への重畳電位が比較器の入力端において等しくできるの
で、本発明を採用するととＫよるルω変換誤差を最も少
なくすることができる。Then, a reference voltage is generated by superimposing a bias voltage at point A and a bias voltage at point B. Each voltage becomes the emitter potential of each transistor 46, 17 via buffer transistors 16, 17. On the other hand, the clamp capacitor is connected to the emitter of the transistor 16 via the switch transistor 11. Therefore, during the synchronous part of the video signal, the switch transistor 1
1 conducts, the transistor 150 pace potential is clamped to the emitter braze of transistor 16. This potential is commonly input to each comparator 6 (255 in the case of 8 pits), so the input flows from the capacitor to the comparator!
, the clamp voltage changes as the current increases. To prevent this, each comparator 3 is connected via a buffer 7 transistor 13.
This is the input. As a result, the base potential of the input terminal and the emitter potential of the output terminal of the buffer transistor 15 are approximately 0.
．． A base-emitter voltage drop of 7 volts occurs, creating a disadvantageous difference with the emitter potential of biased transistor 16. Therefore, the bias potential is dropped by the diode 14 by a voltage equal to the base-emitter voltage of the transistor 15. In addition, if only the bias potential is dropped, a voltage larger than the reference voltage from the Zener diode 12 by the diode sending voltage is applied to both ends of the voltage dividing resistor 20, so in order to compensate for this, a voltage is applied to the voltage dividing resistor 2 via the diode 15. A reference voltage is applied. In the above configuration, a bias voltage is applied to each comparator in the same phase, a comparison operation can be performed using a reference voltage from the Zener diode 12, and the comparator can be operated using a single power source. Furthermore, this embodiment is suitable for semiconductor integrated circuits, and by integration, the paper pressure between the pace and emitter of transistors 16 and 17 and transistor 15 and diode 14. can. Since the clamp potential caused by each droplet bias supply and the superimposed potential on the reference voltage can be made equal at the input end of the comparator, the le ω conversion error due to K can be minimized when the present invention is adopted.
本発明によれば、−電源で動作する比較器にてルω変換
器を構成することができるので、経済的であるばかシか
、装置の小形化にも効果がある。According to the present invention, since the ω converter can be configured with a comparator that operates on a negative power supply, it is not only economical but also effective in reducing the size of the device.
第１図は従来の、νの変換器の構成図、第２図Ｆｉルの
変換器を構成する比較器の回路図、第６図は本発明の一
実施例によるルの変換器の要部を示す回路図、第４図は
本発明を説明づ°るためのビデオ信号を表わす波形図、
第５図Ｖま本発明の他の実施例によるルω変換器の要部
を示す回路図である。
１・・・基準電圧を与える電圧源、
２・・・分圧抵抗、 ３・・・比較器。
８・・・バイアス送圧を与える電圧源、９・・・クラン
プ用スイッチ、
１０・・・クランプ用コンデフザ、
１２・・・ツェナーダイオード。
１５．１６．１７・・・バッファトランジスタ。
１４．１５・・・補償用ダイオード。
才３図
才 ４ 図FIG. 1 is a block diagram of a conventional ν converter, FIG. 2 is a circuit diagram of a comparator that constitutes a FI converter, and FIG. 6 is a main part of a FI converter according to an embodiment of the present invention. FIG. 4 is a waveform diagram representing a video signal for explaining the present invention.
FIG. 5 is a circuit diagram showing a main part of a ω converter according to another embodiment of the present invention. 1... Voltage source that provides a reference voltage, 2... Voltage dividing resistor, 3... Comparator. 8... Voltage source for applying bias pressure, 9... Switch for clamp, 10... Condefuser for clamp, 12... Zener diode. 15.16.17...Buffer transistor. 14.15...Compensation diode. 3rd figure 4th figure
Claims (1)
源とその分圧抵抗とを含む、４．／ｌ）変換器において
、前記比較器の基準電位にバイアス電圧を重畳する手段
と、アナログ入力信号にクランプ電位を与えるクランプ
用コンデンサと、前記コンデンサと前記バイアス電圧を
与える電圧源とを接続する入力信号の同期部の時刻のみ
に導通するスイッチとが設けられていることを特徴とす
るビデオ信号用アナログ−デジタル変換器。1. It includes a comparator, a reference voltage source that provides a reference potential to the comparator, and its voltage dividing resistor; 4. /l) In the converter, means for superimposing a bias voltage on the reference potential of the comparator, a clamping capacitor for providing a clamping potential to the analog input signal, and an input for connecting the capacitor and a voltage source for providing the bias voltage. 1. An analog-to-digital converter for video signals, comprising a switch that is conductive only at the time of a synchronized portion of the signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10971082A JPS592432A (en) | 1982-06-28 | 1982-06-28 | Analog-digital converter for video signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10971082A JPS592432A (en) | 1982-06-28 | 1982-06-28 | Analog-digital converter for video signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS592432A true JPS592432A (en) | 1984-01-09 |
Family
ID=14517250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10971082A Pending JPS592432A (en) | 1982-06-28 | 1982-06-28 | Analog-digital converter for video signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS592432A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01318431A (en) * | 1988-06-20 | 1989-12-22 | Toshiba Corp | Analog/digital converting circuit |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5323553A (en) * | 1976-08-18 | 1978-03-04 | Toshiba Corp | Encoder circu it |
| JPS5374314A (en) * | 1976-12-14 | 1978-07-01 | Nec Corp | Transmitting system for composite video signal |
-
1982
- 1982-06-28 JP JP10971082A patent/JPS592432A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5323553A (en) * | 1976-08-18 | 1978-03-04 | Toshiba Corp | Encoder circu it |
| JPS5374314A (en) * | 1976-12-14 | 1978-07-01 | Nec Corp | Transmitting system for composite video signal |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01318431A (en) * | 1988-06-20 | 1989-12-22 | Toshiba Corp | Analog/digital converting circuit |
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