JPH0419880Y2 - - Google Patents
Info
- Publication number
- JPH0419880Y2 JPH0419880Y2 JP1983146914U JP14691483U JPH0419880Y2 JP H0419880 Y2 JPH0419880 Y2 JP H0419880Y2 JP 1983146914 U JP1983146914 U JP 1983146914U JP 14691483 U JP14691483 U JP 14691483U JP H0419880 Y2 JPH0419880 Y2 JP H0419880Y2
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- differential operational
- circuit
- resistor
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 20
- 230000008929 regeneration Effects 0.000 claims description 4
- 238000011069 regeneration method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 7
- 230000005669 field effect Effects 0.000 description 4
- 230000001360 synchronised effect Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
Description
【考案の詳細な説明】
〔考案の属する技術分野〕
本考案は交流結合回路を経由して入力する映像
信号から直流レベルを再生する回路の改良に関す
る。[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to an improvement of a circuit that reproduces a DC level from a video signal input via an AC coupling circuit.
コンデンサその他の交流結合回路を経由して入
力する映像信号は、零レベルがほぼ信号の平均レ
ベルになつている。この信号から、一般には映像
信号のブランキングレベルが零レベルになるよう
に直流レベルを再生することが必要である。
The zero level of a video signal input via a capacitor or other AC coupling circuit is approximately the average level of the signal. From this signal, it is generally necessary to reproduce the DC level so that the blanking level of the video signal becomes zero level.
第１図にこのための従来例回路を示す。この回
路は入力信号を抵抗器R11を介して差動演算増幅
器A11の反転入力に与え、出力信号をこの差動演
算増幅器A11の出力から得る。このとき差動演算
増幅器A11には抵抗器R12により負帰還を与えて
おく。出力信号を抵抗器R13で分岐して、スイツ
チ回路Ｓを介して非反転入力が共通電位点に接続
された差動演算増幅器A12に与える。この差動演
算増幅器A12の出力は差動演算増幅器A11の非反
転入力に接続し、この非反転入力と差動演算増幅
器A12の反転入力との間にはコンデンサC11が接
続される。 FIG. 1 shows a conventional circuit for this purpose. This circuit provides an input signal through a resistor R 11 to the inverting input of a differential operational amplifier A 11 and obtains an output signal from the output of this differential operational amplifier A 11 . At this time, negative feedback is provided to the differential operational amplifier A11 by a resistor R12 . The output signal is branched by a resistor R13 and applied via a switch circuit S to a differential operational amplifier A12 whose non-inverting input is connected to a common potential point. The output of this differential operational amplifier A 12 is connected to the non-inverting input of the differential operational amplifier A 11 , and a capacitor C 11 is connected between this non-inverting input and the inverting input of the differential operational amplifier A 12 . .
この回路では、スイツチ回路Ｓを入力信号に接
続された同期分離回路SYの出力で制御して、同
期信号のタイミングで差動演算増幅器A11の非反
転入力を直流零レベルに保持する。 In this circuit, the switch circuit S is controlled by the output of the synchronous separation circuit SY connected to the input signal, and the non-inverting input of the differential operational amplifier A11 is held at DC zero level at the timing of the synchronous signal.
この従来例回路は、同期分離回路SYが必要で
あること、スイツチ回路Ｓとしてアナログ・スイ
ツチが必要であることなど、特殊な部品を必要と
して回路構成が複雑になる欠点がある。 This conventional circuit has the drawback that it requires special parts, such as the need for a synchronous separation circuit SY and the need for an analog switch as the switch circuit S, resulting in a complicated circuit configuration.
第２図は回路を簡単化した従来例回路である。
この例は、入力信号をコンデンサC12およびバツ
フア増幅回路A13を介して出力に結合するととも
に、バツフア増幅回路A13と並列に差動演算増幅
器A14を接続して、その出力をダイオードD11を
介してその差動演算増幅器A14に接続する。 FIG. 2 shows a conventional circuit with a simplified circuit.
In this example, the input signal is coupled to the output via capacitor C 12 and buffer amplifier circuit A 13 , and a differential operational amplifier A 14 is connected in parallel with buffer amplifier circuit A 13 , and its output is coupled to the output through diode D 11. connect to its differential operational amplifier A14 through.
この回路では映像信号のブランキング期間にダ
イオードD11が導通して、差動演算増幅器A14に
強い負帰還がかかり、バツフア増幅回路A13の入
力に直流零レベルを与える。これがコンデンサ
C12に保持されて、直流レベルを再生するように
構成された回路である。この回路は構成が簡単で
はあるが、バツフア増幅回路A13としてオフセツ
ト電圧がなく周波数帯域の広いものが必要であ
り、ブランキング期間に入力がコンデンサC12を
介して短絡されることになるので、ブランキン
グ・レベルが正確に固定できない。さらに、反転
出力を得るために、出力にもう１段の反転増幅器
を接続しなければならないなどの欠点がある。 In this circuit, the diode D11 conducts during the blanking period of the video signal, and strong negative feedback is applied to the differential operational amplifier A14 , giving a DC zero level to the input of the buffer amplifier circuit A13 . This is the capacitor
C 12 is a circuit configured to reproduce the DC level. Although this circuit has a simple configuration, it requires a buffer amplifier circuit A 13 with no offset voltage and a wide frequency band, and the input is short-circuited via the capacitor C 12 during the blanking period. The blanking level cannot be fixed accurately. Furthermore, there are drawbacks such as the need to connect another stage of inverting amplifier to the output in order to obtain an inverted output.
本考案はこれを改良するもので、特殊な部品を
必要とせず、回路構成が簡単であり、同期信号な
ど外部の信号を必要とせず、さらに動作の確実な
直流再生回路を提供することを目的とする。
The purpose of this invention is to improve this, and to provide a DC regeneration circuit that does not require special parts, has a simple circuit configuration, does not require external signals such as synchronization signals, and has reliable operation. shall be.
本考案は、非反転入力が共通電位点に接続され
た差動演算増幅器と、一端が信号入力に接続され
他端が上記差動演算増幅器の反転入力に接続され
た第一の抵抗器と、一端が上記差動演算増幅器の
反転入力に接続され他端が信号出力に接続された
第二の抵抗器と、上記信号出力にアノードが接続
され上記差動演算増幅器の出力にカソードが接続
された第一のダイオードと、上記差動演算増幅器
の出力にアノードが接続された第二のダイオード
と、この第二のダイオードのカソードと共通電位
点との間に接続されたコンデンサと、上記第二の
ダイオードのカソードと上記差動演算増幅器の反
転入力との間に接続された第三の抵抗器とを備え
た構成を特徴とする。
The present invention comprises: a differential operational amplifier having a non-inverting input connected to a common potential point; a first resistor having one end connected to a signal input and the other end connected to an inverting input of the differential operational amplifier; a second resistor having one end connected to the inverting input of the differential operational amplifier and the other end connected to the signal output; an anode connected to the signal output and a cathode connected to the output of the differential operational amplifier; a first diode, a second diode whose anode is connected to the output of the differential operational amplifier, a capacitor connected between the cathode of the second diode and the common potential point, and the second diode. The present invention is characterized by a configuration including a third resistor connected between the cathode of the diode and the inverting input of the differential operational amplifier.
第３図は本考案第一実施例回路の構成図であ
る。入力端子INは抵抗器R0で終端され第一の抵
抗器R1を介して、差動演算増幅器A1の反転入力
に接続する。この差動演算増幅器A1の非反転入
力は共通電位点に接続する。さらにこの差動演算
増幅器A1の反転入力は第二の抵抗器R2を介して
出力端子OUTに接続する。出力端子OUTと差動
演算増幅器A1との間には第一のダイオードD1を
接続し、差動演算増幅器A1の出力と共通電位点
との間には第二のダイオードD2とコンデンサC1
の直列回路を接続する。このダイオードD2とコ
ンデンサC1との接続点と差動演算増幅器A1の反
転入力との間には第三の抵抗器R3を接続する。
FIG. 3 is a block diagram of a circuit according to a first embodiment of the present invention. The input terminal IN is terminated with a resistor R 0 and connected to the inverting input of the differential operational amplifier A 1 via a first resistor R 1 . The non-inverting input of this differential operational amplifier A1 is connected to a common potential point. Further, the inverting input of this differential operational amplifier A1 is connected to the output terminal OUT via a second resistor R2 . A first diode D1 is connected between the output terminal OUT and the differential operational amplifier A1 , and a second diode D2 and a capacitor are connected between the output of the differential operational amplifier A1 and the common potential point. C 1
Connect the series circuit. A third resistor R3 is connected between the connection point between the diode D2 and the capacitor C1 and the inverting input of the differential operational amplifier A1 .
このように構成された回路の動作を第４図に示
す信号波形図を用いて説明する。第４図ａは入力
端子INの信号波形を示し、同ｂは出力端子OUT
の信号波形を示す。 The operation of the circuit configured in this way will be explained using the signal waveform diagram shown in FIG. Figure 4a shows the signal waveform at the input terminal IN, and figure 4b shows the signal waveform at the output terminal OUT.
The signal waveform of is shown.
ブランキング期間T1では、入力電圧は負であ
るので、コンデンサC1および抵抗器R3を介して、
抵抗器R1には第３図に示す左向きの電流i1が流れ
る。したがつて、差動演算増幅器A1の出力は正
になり、第一のダイオードD1は遮断、第二のダ
イオードD2は導通の状態になる。このときダイ
オードD1遮断状態であり、差動演算増幅器A1に
は導通状態のダイオードD2および抵抗器R3を介
して大きい負帰還がかかり、差動演算増幅器A1
の正負入力は等しい電圧すなわち零電位になるの
で、出力端子OUTの電位は抵抗器R2を介して零
になる。このとき抵抗器R3にも抵抗器R1と等し
い電流i1が流れるので、コンデンサC1の端子電圧
Vcは
Vc＝i1R3＝R3／R1・Vb ……(1)
でなければならない。すなわち、コンデンサC1
は差動増幅器A1よりダイオードD2を介して上記
(1)式を満足するように充電される。 In the blanking period T 1 , the input voltage is negative, so through the capacitor C 1 and resistor R 3 ,
A leftward current i 1 shown in FIG. 3 flows through the resistor R 1 . Therefore, the output of the differential operational amplifier A1 becomes positive, the first diode D1 is cut off, and the second diode D2 is turned on. At this time, the diode D1 is in the cutoff state, and a large negative feedback is applied to the differential operational amplifier A1 through the conductive diode D2 and the resistor R3 , and the differential operational amplifier A1
Since the positive and negative inputs of are at equal voltage, that is, zero potential, the potential at the output terminal OUT becomes zero via resistor R2 . At this time, a current i 1 equal to that of resistor R 1 flows through resistor R 3 as well, so the terminal voltage of capacitor C 1
Vc must be Vc=i 1 R 3 = R 3 /R 1・Vb (1). i.e. capacitor C 1
is the above differential amplifier A 1 through diode D 2
It is charged to satisfy equation (1).
つぎに映像信号の期間T2では、入力電圧が正
になるので、抵抗器R1には第３図に示す右向き
の電流i2が流れ、第一のダイオードD1が導通状態
になり、第二のダイオードD2が遮断の状態にな
る。したがつて、差動演算増幅器A1には抵抗器
R2を介して負帰還がかかる。この期間T2ではコ
ンデンサC1が差動演算増幅器A1の反転入力に電
圧Vcを与え続けるので、入力電圧には−Vbが加
算されて直流成分が再生されたことになる。映像
信号は差動演算増幅器A1により反転されて、出
力端子OUTには第４図ｂに示す信号が現れる。 Next, during the video signal period T2 , the input voltage becomes positive, so the rightward current i2 shown in FIG. 3 flows through the resistor R1 , the first diode D1 becomes conductive, and the first diode D1 becomes conductive. The second diode D2 becomes cut off. Therefore, the differential operational amplifier A1 has a resistor
Negative feedback is applied via R2 . During this period T2 , the capacitor C1 continues to apply the voltage Vc to the inverting input of the differential operational amplifier A1 , so that -Vb is added to the input voltage and the DC component is regenerated. The video signal is inverted by the differential operational amplifier A1 , and the signal shown in FIG. 4b appears at the output terminal OUT.
負帰還が施された差動演算増幅器の電流利得は
負帰還抵抗の値に等しくなるので、出力端子
OUTの電圧Ｅは
Ｅ＝−R2／R1Vv−R2／R3Vc＝−R2／R1（Vb＋Vv）
……(2)
となり直流成分が再生されたことが分る。ここ
で、Vvは入力信号の映像信号の零レベルからの
値、Vbは入力信号のブランキング・レベルの零
レベルからの大きさ、VcはコンデンサC1の端子
電圧である。 The current gain of a differential operational amplifier with negative feedback is equal to the value of the negative feedback resistor, so the output terminal
The OUT voltage E is E=-R 2 /R 1 Vv-R 2 /R 3 Vc=-R 2 /R 1 (Vb+Vv) (2), which shows that the DC component has been regenerated. Here, Vv is the value of the input signal from the zero level of the video signal, Vb is the magnitude of the blanking level of the input signal from the zero level, and Vc is the terminal voltage of the capacitor C1 .
第３図の回路では、映像信号の期間T2にコン
デンサC1の電荷が抵抗器R3を介して放電される
と、出力波形にサグが生じるが、時定数C1R3を
入力信号の繰り返し周期より十分に大きくしてお
けば、実用上の問題はない。 In the circuit shown in Figure 3, when the charge in the capacitor C 1 is discharged through the resistor R 3 during the video signal period T 2 , a sag occurs in the output waveform. If it is made sufficiently larger than the repetition period, there will be no practical problem.
第５図は本考案第二実施例回路の構成図であ
る。この例は第３図の回路と比べると、コンデン
サC1と抵抗器R3との間に電界効果トランジスタ
Q1によるバツフア増幅回路を挿入したところに
特徴がある。すなわち第二のダイオードD2とコ
ンデンサC1との接続点を電界効果トランジスタ
Q1のゲートに接続する。この電界効果トランジ
スタQ1のソースを抵抗器R4により共通電位点に
接続して、この電界効果トランジスタQ1をソー
スフオロワ回路として、このソースに抵抗器R3
を接続する。その他の構成は第３図で説明したも
のと同様である。 FIG. 5 is a block diagram of a circuit according to a second embodiment of the present invention. Compared to the circuit in Figure 3, this example has a field effect transistor between capacitor C 1 and resistor R 3 .
The feature is that a buffer amplification circuit based on Q1 is inserted. That is, the connection point between the second diode D 2 and the capacitor C 1 is a field effect transistor
Connect to the gate of Q1 . The source of this field effect transistor Q 1 is connected to a common potential point by a resistor R 4 , and this field effect transistor Q 1 is used as a source follower circuit, and a resistor R 3 is connected to this source.
Connect. The other configurations are the same as those explained in FIG. 3.
この構成により、コンデンサC1の電荷が映像
信号の期間T2に放電されることがなく、出力波
形は忠実に再現される。その他の動作は第３図お
よび第４図で説明した第一実施例と同様である。 With this configuration, the charge in the capacitor C1 is not discharged during the video signal period T2 , and the output waveform is faithfully reproduced. Other operations are similar to those of the first embodiment described in FIGS. 3 and 4.
以上説明したように、本考案によれば、特殊な
部品を必要とせず、回路構成が簡単であり、同期
信号など外部の信号を必要とせず、さらに動作の
確実な直流再生回路を得ることができる。この回
路は、出力回路にダイオードが接続されていて出
力端子に正の電圧が送出されることがないので、
正の電圧が入力されると入力回路が破壊されるビ
デオ信号用のアナログ・デイジタル変換回路の前
段に接続して使用するとき、保護回路となつて極
めて有用である。
As explained above, according to the present invention, it is possible to obtain a DC regeneration circuit that does not require special parts, has a simple circuit configuration, does not require external signals such as synchronization signals, and has reliable operation. can. This circuit has a diode connected to the output circuit and no positive voltage is sent to the output terminal, so
It is extremely useful as a protection circuit when connected to the front stage of an analog-to-digital conversion circuit for video signals, where the input circuit is destroyed if a positive voltage is input.
第１図は従来例回路の構成図。第２図は従来例
回路の構成図。第３図は本考案第一実施例回路の
構成図。第４図はその動作説明用のタイムチヤー
ト。ａは入力信号の波形を示し、ｂは出力信号の
波形を示す。第５図は本考案第二実施例回路の構
成図。
FIG. 1 is a configuration diagram of a conventional circuit. FIG. 2 is a configuration diagram of a conventional circuit. FIG. 3 is a block diagram of the circuit according to the first embodiment of the present invention. Figure 4 is a time chart for explaining its operation. a indicates the waveform of the input signal, and b indicates the waveform of the output signal. FIG. 5 is a block diagram of a circuit according to a second embodiment of the present invention.
Claims (1)
算増幅器A1と、 一端が信号入力に接続され他端が上記差動演
算増幅器の反転入力に接続された第一の抵抗器
R1と、 一端が上記差動演算増幅器の反転入力に接続
され他端が信号出力に接続された第二の抵抗器
R2と、 上記信号出力にアノードが接続され上記差動
演算増幅器の出力にカソードが接続された第一
のダイオードD1と、 上記差動演算増幅器の出力にアノードが接続
された第二のダイオードD2と、 この第二のダイオードのカソードと共通電位
点との間に接続されたコンデンサC1と、 上記第二のダイオードのカソードと上記差動
演算増幅器の反転入力との間に接続された第三
の抵抗器R3と を備えた直流再生回路。 (2) コンデンサと第三の抵抗器との間にバツフア
増幅回路が挿入された実用新案登録請求の範囲
第(1)項に記載の直流再生回路。[Claims for Utility Model Registration] (1) A differential operational amplifier A1 whose non-inverting input is connected to a common potential point, and one end connected to the signal input and the other end connected to the inverting input of the differential operational amplifier. The first resistor
R 1 and a second resistor with one end connected to the inverting input of the differential operational amplifier and the other end connected to the signal output.
R 2 , a first diode D 1 having an anode connected to the signal output and a cathode connected to the output of the differential operational amplifier; and a second diode D 1 having an anode connected to the output of the differential operational amplifier. D2 , a capacitor C1 connected between the cathode of this second diode and the common potential point, and a capacitor C1 connected between the cathode of the second diode and the inverting input of the differential operational amplifier. DC regeneration circuit with a third resistor R 3 . (2) The DC regeneration circuit according to claim (1) of the utility model registration, in which a buffer amplifier circuit is inserted between the capacitor and the third resistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14691483U JPS6055160U (en) | 1983-09-21 | 1983-09-21 | DC regeneration circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14691483U JPS6055160U (en) | 1983-09-21 | 1983-09-21 | DC regeneration circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6055160U JPS6055160U (en) | 1985-04-18 |
| JPH0419880Y2 true JPH0419880Y2 (en) | 1992-05-07 |
Family
ID=30326863
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14691483U Granted JPS6055160U (en) | 1983-09-21 | 1983-09-21 | DC regeneration circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6055160U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0793698B2 (en) * | 1985-11-13 | 1995-10-09 | キヤノン株式会社 | Feed back clamp circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53140342U (en) * | 1977-04-13 | 1978-11-06 | ||
| JPS55150515U (en) * | 1979-04-14 | 1980-10-30 |
-
1983
- 1983-09-21 JP JP14691483U patent/JPS6055160U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6055160U (en) | 1985-04-18 |
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| JPS58161424A (en) | Switching circuit |