JPS62111516A - Pulse width automatic correction circuit - Google Patents
Pulse width automatic correction circuitInfo
- Publication number
- JPS62111516A JPS62111516A JP25154485A JP25154485A JPS62111516A JP S62111516 A JPS62111516 A JP S62111516A JP 25154485 A JP25154485 A JP 25154485A JP 25154485 A JP25154485 A JP 25154485A JP S62111516 A JPS62111516 A JP S62111516A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- pulse width
- circuit
- terminal
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
- H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold
- H03K5/086—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback
- H03K5/088—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold generated by feedback modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発四はパルス幅自動補正回路に係り、特に、平均直流
パルスが一定のデジタル信号のパルス幅対称性をレベル
変動に応じて補正して取出す回路に関する。[Detailed Description of the Invention] Industrial Application Field The present invention relates to an automatic pulse width correction circuit, and in particular, a circuit that corrects and extracts the pulse width symmetry of a digital signal with a constant average DC pulse according to level fluctuations. Regarding.
従来の技術
一般に、テレビジョン信号の垂直ブランキング期間にデ
ジタル信号情報を重畳する場合、デジタル信号の周波数
帯域を制限するためにその立上り及び立下りは正弦２乗
特性になっている。このようなデジタル信号を重畳され
たテレビジョン信号を受信してデジタル信号を取出すに
際し、従来、電圧コーンパレータにて比較’６３１モと
比較することによって得ているのは周知である。2. Description of the Related Art In general, when digital signal information is superimposed on the vertical blanking period of a television signal, the rising and falling edges thereof have sinusoidal square characteristics in order to limit the frequency band of the digital signal. It is well known that when receiving a television signal on which such a digital signal is superimposed and extracting the digital signal, the digital signal is conventionally obtained by comparing it with a '631 model using a voltage cone comparator.
発明が解決しようとする問題点
従来のものは上記電圧コンパレータの比較電圧が一定で
あるため、入力信号レベルが変動するとこれに伴って出
力デジタル信号のパルス幅対称性（デユーティ比）が変
動して正確なデジタル情報を得ることができない。そこ
で、電圧コンパレータの前に自動レベル制御回路（ＡＬ
Ｃ＞を設けて入力信号レベルを一定になるようにしてい
るが、回路が大形化し、安価に描成し得ない問題点があ
った。Problems to be Solved by the Invention In the conventional system, the comparison voltage of the voltage comparator is constant, so when the input signal level changes, the pulse width symmetry (duty ratio) of the output digital signal changes accordingly. Unable to obtain accurate digital information. Therefore, an automatic level control circuit (AL) is installed before the voltage comparator.
C> is provided to keep the input signal level constant, but there is a problem that the circuit becomes large and cannot be drawn at low cost.
本発明は、入力レベル変動に拘らずパルス幅対称性を一
定にして取出し得るパルス幅自動補正回路を提供するこ
とを目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide an automatic pulse width correction circuit that can maintain constant pulse width symmetry regardless of input level fluctuations.
問題点を解決するための手段
第１図において、電圧コンパレータ２はその一入力端子
にその出力平均直流レベルに応じてレベル変化する比較
電位を供給される電圧比較手段の一実施例である。Means for Solving the Problems In FIG. 1, a voltage comparator 2 is an embodiment of a voltage comparing means whose one input terminal is supplied with a comparison potential whose level changes in accordance with its output average DC level.
作用
電圧コンパレータ２の出力の平均直流レベルを比較電位
Ｖｓ 、 Ｖｓ ’ としてその他方の入力端子にフィ
ードバック供給し、電圧コンパレータ２の出力端子から
パルス幅補＋Ｅデジタル信号を取出す。The average DC level of the output of the working voltage comparator 2 is fed back to the other input terminal as comparison potentials Vs and Vs', and a pulse width complementary +E digital signal is taken out from the output terminal of the voltage comparator 2.
実施例 第１図は本発明回路の一実施例の回路図を示す。Example FIG. 1 shows a circuit diagram of an embodiment of the circuit of the present invention.
同図にＪ３いて、端子１に入来したデジタル信号を重畳
されたテレビジョン入力信号ａ（第２図（八））（デジ
タル信号は平均直流レベルが一定のいわゆるパイ・フェ
ーズ・コードとする）はコンデンサＣ１を経た後ダイオ
ードＤ、！：電源Ｅｌとによって電位Ｆ１に同期信号先
端をクランプされ、電圧コンパレータ２の＋入力端子に
供給されてその一入力端子に供給される比較電位Ｖ５と
比較され、アンドゲート３にて後）ホのゲート信号ｂ（
同図（Ｂ））とアンドをとられて端子４よりデジタル信
号Ｃ（同図（Ｃ））として取出される。At J3 in the same figure, the television input signal a (Fig. 2 (8)) on which the digital signal input to terminal 1 is superimposed (the digital signal is a so-called pi-phase code with a constant average DC level) passes through capacitor C1 and then diode D, ! : The tip of the synchronizing signal is clamped to the potential F1 by the power supply El, and is supplied to the + input terminal of the voltage comparator 2, and compared with the comparison potential V5 supplied to its one input terminal. Gate signal b (
(B) in the same figure) and is taken out from the terminal 4 as a digital signal C ((C) in the same figure).
この場合、端子５に入来した垂直ブランキング期間に対
応したパルス幅をもつゲート信号ｂ＜同図＜８））はア
ンドゲート３に供給されて電圧コンパレータ２の出力と
アンドをとられる一方、スイッチ回路６に供給されてこ
れをオンせしめる。In this case, the gate signal b<8)) having a pulse width corresponding to the vertical blanking period that has entered the terminal 5 is supplied to the AND gate 3 and ANDed with the output of the voltage comparator 2. The signal is supplied to the switch circuit 6 to turn it on.
これにより、信号Ｃはスイッチ回路６を介して抵抗Ｒ及
びコンデンサＣにて構成される積分回路７にて供給され
て直流電位Ｖ４ （同図（Ｃ））に変換され、アンプ
８にて比較電位Ｖｓ （同図（Ａ））とされて電圧コ
ンパレータ２の一入力端子に供給される。なお、入力信
号が第２図（Ａ）に実線（ａ）で示す正規状態のとき、
Ｖ４ ＝Ｅ２ ＝Ｖ５になるように設定されている（第
１図では、ｖ４＝Ｅｚのときアンプ８の出力は零になる
ので、アンプ８の出力に等制約に電源Ｅｚ （−Ｖｓ
）の記号を記す）。As a result, the signal C is supplied via the switch circuit 6 to the integrating circuit 7 composed of a resistor R and a capacitor C, where it is converted to a DC potential V4 ((C) in the same figure), and the amplifier 8 supplies the signal C to a comparison potential V4. Vs ((A) in the figure) and is supplied to one input terminal of the voltage comparator 2. Note that when the input signal is in the normal state shown by the solid line (a) in Fig. 2 (A),
It is set so that V4 = E2 = V5 (in Fig. 1, when v4 = Ez, the output of amplifier 8 becomes zero, so the output of amplifier 8 is set to be equal to power supply Ez (-Vs
).
ここで、入ノＪ信号が第２図（Ａ）に破Ｉ！（ａ’）で
示す状態に低下したとすると、この瞬間アンプ８の＋入
力端子はまだ電位ｖ４を保持しているので電圧コンパレ
ータ２の一入力端子Ｖ５であり、出力信号ｄは第２図（
Ｄ）のようになる。信号ｄは積分回路７にて直流電位Ｖ
４′ （同図（Ｄ））に変換され、アンプ８にて（ＶＩ
’ −Ｅ２ ）なる電在に応じた比較電位ｖ５′ （同
図（Ａ））どされる。Here, the incoming J signal breaks I! in Figure 2 (A). Assuming that the voltage drops to the state shown in (a'), the + input terminal of the instantaneous amplifier 8 still holds the potential v4, so it is one input terminal V5 of the voltage comparator 2, and the output signal d is as shown in FIG.
D). The signal d is converted to a DC potential V by the integrating circuit 7.
4' ((D) in the same figure), and is converted into (VI
The comparison potential v5' ((A) in the same figure) is returned according to the electric current of '-E2).
従って、積分回路７の抵抗Ｒ及びコンデンサＣの時定数
Ｊ：り十分時間が経過し！ζ後は同図（Ｃ）に示す出力
信号Ｃが取出され、正規状態と殆ど同じ波形になり、パ
ルス幅対称性が保持される。これは、入力信号の波形が
歪んでいる場合も同様の＋）３作によりパルス幅対称性
を保持し１！？る。Therefore, enough time has passed for the time constant J of the resistor R and capacitor C of the integrating circuit 7! After ζ, the output signal C shown in FIG. 3(C) is taken out and has almost the same waveform as in the normal state, and the pulse width symmetry is maintained. Even when the waveform of the input signal is distorted, the pulse width symmetry is maintained by the same +)3 operation and 1! ? Ru.
第３図は本発明回路の他の実施例の回路図を示し、同図
中、第１図と同一部分には同一番号を付してその説明を
省略する。このものは、６２５本走査線方式のテレビジ
ョン信号の第１６番目の水平走査線（垂直ブランキング
１刀間）にデジタル情報を重畳したものに適用される。FIG. 3 shows a circuit diagram of another embodiment of the circuit of the present invention, in which the same parts as in FIG. 1 are given the same numbers and their explanations will be omitted. This method is applied to a 625-scanning-line television signal in which digital information is superimposed on the 16th horizontal scanning line (vertical blanking interval).
端子５′に入来した第１６番目のラインを示すゲートパ
ルスｂ′はトランジスタＱ２、抵抗Ｒ６にて構成される
アナログスイッチ回路９に供給されてこれをオンせしめ
、これにより、電圧コンパレータ２から取は１された信
号はインバータ回路１０、抵抗Ｒ５、スイッチ回路９を
介してコンデンサＣ４に供給されて積分され、トランジ
スタＱ１を介して電圧コンパレータ２の一入力端子に比
較電位として供給される。The gate pulse b' indicating the 16th line inputted to the terminal 5' is supplied to the analog switch circuit 9 composed of the transistor Q2 and the resistor R6 and turns it on. The signal which is set to 1 is supplied to the capacitor C4 via the inverter circuit 10, the resistor R5, and the switch circuit 9, where it is integrated, and then supplied to one input terminal of the voltage comparator 2 as a comparison potential via the transistor Q1.
この場合、端子５″に入来したゲートパルスｂ′と逆極
性のゲートパルスｌ） ｎはコンデンサＣ３及びトラン
ジスタＱ１にてクランプされる。In this case, the gate pulse l)n having the opposite polarity to the gate pulse b' entering the terminal 5'' is clamped by the capacitor C3 and the transistor Q1.
このように、電圧コンパレータ２の一入力端子にゲート
パルスｂ ″期間比較電位を供給しているので、第１図
に示ずアンドゲート３を設ける必要はない。In this way, since the gate pulse b'' period comparison potential is supplied to one input terminal of the voltage comparator 2, there is no need to provide the AND gate 3 not shown in FIG.
第３図において、抵抗Ｒ＋ 、Ｒ２の比及び抵抗Ｒ４，
Ｒｓの比により正規状態での出力レベルＶ２を設定する
。この場合、入力信号レベルｖ１が出力レベルｖ２に比
して小に設定されるので、第１図に示すアンプ８を設け
る必要はない。In FIG. 3, the ratio of resistances R+, R2 and resistances R4,
The output level V2 in the normal state is set by the ratio of Rs. In this case, since the input signal level v1 is set lower than the output level v2, there is no need to provide the amplifier 8 shown in FIG. 1.
発明の効果
本発明回路によれば、電圧コンパレータの比較電位が入
力レベルに応じて変化するので、出力デジタル信号のパ
ルス幅対称性を一定に保持し得、特に、電圧コンパレー
タの前に自動レベル１７３１１１回路を設けて入力レベ
ルを１ＩＩＪ１［ｌする必要がなく、回路を小形化し得
、安価に構成し得る等の特長を有する。Effects of the Invention According to the circuit of the present invention, since the comparison potential of the voltage comparator changes according to the input level, the pulse width symmetry of the output digital signal can be kept constant. It has the advantage that there is no need to provide a circuit to set the input level to 1IIJ1[l, the circuit can be made smaller, and it can be constructed at low cost.
第１図及び第２図は夫々本発明回路の一実施例の回路図
及びその信号波形図、第３図は本発明回路の他の実施例
の回路図である。
１・・・デレビジミン信号入力端子、２・・・電圧コン
パレータ、３・・・アンドゲート、４・・・デジタル信
号出力端子、５・・・ゲートパルス入力端子、６・・・
スイッチ回路、７・・・積分回路、８・・・アンプ。
第１図
第３図1 and 2 are circuit diagrams and signal waveform diagrams of one embodiment of the circuit of the present invention, respectively, and FIG. 3 is a circuit diagram of another embodiment of the circuit of the present invention. DESCRIPTION OF SYMBOLS 1... Derevidimin signal input terminal, 2... Voltage comparator, 3... AND gate, 4... Digital signal output terminal, 5... Gate pulse input terminal, 6...
Switch circuit, 7...integrator circuit, 8...amplifier. Figure 1 Figure 3
Claims (1)
一定のデジタル信号を供給し、誘電圧コンパレータの出
力の平均直流レベルを比較電位として該電圧コンパレー
タの他方の入力端子にフィードバック供給し、該電圧コ
ンパレータの出力端子からパルス幅補正デジタル信号を
取出す構成としてなることを特徴とするパルス幅自動補
正回路。A digital signal with a constant average DC level is supplied to one input terminal of the voltage comparator, and the average DC level of the output of the dielectric voltage comparator is fed back as a comparison potential to the other input terminal of the voltage comparator. A pulse width automatic correction circuit characterized in that it is configured to take out a pulse width correction digital signal from an output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25154485A JPS62111516A (en) | 1985-11-09 | 1985-11-09 | Pulse width automatic correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25154485A JPS62111516A (en) | 1985-11-09 | 1985-11-09 | Pulse width automatic correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62111516A true JPS62111516A (en) | 1987-05-22 |
Family
ID=17224403
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25154485A Pending JPS62111516A (en) | 1985-11-09 | 1985-11-09 | Pulse width automatic correction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62111516A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221548A (en) * | 1994-01-31 | 1995-08-18 | Nippon Precision Circuits Kk | Oscillation use integrated circuit and oscillation |
| US6031404A (en) * | 1996-12-19 | 2000-02-29 | Stmicroelectronics Gmbh | Analog-signal to square-wave-signal reshaping system with offset compensation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56156053A (en) * | 1980-05-02 | 1981-12-02 | Fujitsu Ten Ltd | Waveform shaping circuit |
-
1985
- 1985-11-09 JP JP25154485A patent/JPS62111516A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56156053A (en) * | 1980-05-02 | 1981-12-02 | Fujitsu Ten Ltd | Waveform shaping circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07221548A (en) * | 1994-01-31 | 1995-08-18 | Nippon Precision Circuits Kk | Oscillation use integrated circuit and oscillation |
| US6031404A (en) * | 1996-12-19 | 2000-02-29 | Stmicroelectronics Gmbh | Analog-signal to square-wave-signal reshaping system with offset compensation |
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