JPS582040U - Clock circuit in data processing equipment - Google Patents
Clock circuit in data processing equipmentInfo
- Publication number
- JPS582040U JPS582040U JP7336082U JP7336082U JPS582040U JP S582040 U JPS582040 U JP S582040U JP 7336082 U JP7336082 U JP 7336082U JP 7336082 U JP7336082 U JP 7336082U JP S582040 U JPS582040 U JP S582040U
- Authority
- JP
- Japan
- Prior art keywords
- data processing
- clock circuit
- period
- logic value
- processing equipment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は誤り訂正回路を附加した記憶装置のブロック図
、第２図は本考案の１実施例のブロック図、第３図及び
第４図はそれぞれ第２図の動作を説明する図である。
１５・・・・・・発振器、１６ないし１８・・・・・・
ラリツブ・フロップ、１９．２０・・・・”・・ＡＮＤ
回路、２１・・・・・・ＮＡＮＤＡＮＤ回路・・・・・
・ＯＲ回路、２３・・回合、定ゲート付きＡＮＤ回路、
２４・・・・・・否定回路、＊ＦＣＫ・・曲読出しクロ
ック。FIG. 1 is a block diagram of a storage device equipped with an error correction circuit, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 are diagrams each explaining the operation of FIG. 2. . 15...Oscillator, 16 to 18...
Laritz flop, 19.20..."...AND
Circuit, 21...NANDAND circuit...
・OR circuit, 23...AND circuit with constant gate,
24...Negation circuit, *FCK... Song read clock.
Claims (1)
外部信号が所定値を有していない場合には期間ｔ、□の
間は論理値Ａとなる・と共に上記期間ｔ１よりは長い期
間ｔ２の間は論理値Ａを反転した論理値Ｂとなるような
りロック信号を出力する第１の手段と、上記所定の外部
信号の状態に応じて上記第１の手段を制御する第２の手
段とを備え、且つ上記第１の手段から出力されるクロッ
ク信号の状態が論理値Ａであるときに上記所定の外部信
号が所定値になった場合には、当該論理値Ａの状態を上
記期間ｔ１より長くするように構成されたことを特徴と
するデータ処理装置のクロック回路。In a clock circuit in a data processing device, when a predetermined external signal does not have a predetermined value, the logic value is A during the period t, and the logic value is during the period t2, which is longer than the period t1. a first means for outputting a lock signal such that the logic value B becomes a logical value obtained by inverting A; and a second means for controlling the first means in accordance with a state of the predetermined external signal; If the predetermined external signal reaches a predetermined value when the state of the clock signal output from the first means is the logic value A, the state of the logic value A is made longer than the period t1. A clock circuit for a data processing device, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7336082U JPS5840417Y2 (en) | 1982-05-19 | 1982-05-19 | Clock circuit in data processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7336082U JPS5840417Y2 (en) | 1982-05-19 | 1982-05-19 | Clock circuit in data processing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS582040U true JPS582040U (en) | 1983-01-07 |
| JPS5840417Y2 JPS5840417Y2 (en) | 1983-09-12 |
Family
ID=29869140
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7336082U Expired JPS5840417Y2 (en) | 1982-05-19 | 1982-05-19 | Clock circuit in data processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5840417Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465423U (en) * | 1990-10-19 | 1992-06-08 |
-
1982
- 1982-05-19 JP JP7336082U patent/JPS5840417Y2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0465423U (en) * | 1990-10-19 | 1992-06-08 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5840417Y2 (en) | 1983-09-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS582040U (en) | Clock circuit in data processing equipment | |
| JPS5942640U (en) | flip-flop circuit | |
| JPS5996610U (en) | Bus abnormality detection circuit | |
| JPS6020695U (en) | Input signal detection circuit | |
| JPS59174741U (en) | digital integrated circuit | |
| JPS59130144U (en) | Parity check circuit | |
| JPS5850738U (en) | signal stabilization circuit | |
| JPS59189336U (en) | input circuit | |
| JPS5881655U (en) | comparison circuit | |
| JPS6135437U (en) | Set/reset flip-flop circuit | |
| JPS60100851U (en) | memory device | |
| JPS60145753U (en) | Asynchronous confirmation auxiliary circuit | |
| JPS60636U (en) | multiplication circuit | |
| JPS60109102U (en) | digital control circuit | |
| JPS6133149U (en) | Error information removal device | |
| JPS58107633U (en) | Output circuit | |
| JPS58149822U (en) | flip-flop circuit | |
| JPS601037U (en) | binary circuit | |
| JPS6087040U (en) | digital limiter circuit | |
| JPS5847945U (en) | Request signal processing circuit | |
| JPS6113398U (en) | integrated circuit | |
| JPS58129744U (en) | T flip-flop circuit with priority circuit | |
| JPS5933334U (en) | flip-flop circuit | |
| JPS59134948U (en) | Working/standby switching logic circuit | |
| JPS59119644U (en) | Gate array IC |