JPS5850738U - signal stabilization circuit - Google Patents
signal stabilization circuitInfo
- Publication number
- JPS5850738U JPS5850738U JP13827381U JP13827381U JPS5850738U JP S5850738 U JPS5850738 U JP S5850738U JP 13827381 U JP13827381 U JP 13827381U JP 13827381 U JP13827381 U JP 13827381U JP S5850738 U JPS5850738 U JP S5850738U
- Authority
- JP
- Japan
- Prior art keywords
- value
- counter means
- values
- stabilization circuit
- signal stabilization
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は本考案の一実施例の回路図、第２図はそのタイ
ミングチャート。
１．９・・・・・・フリップフロップ、２，３．４．５
・・・・・・ゲート ６−−−−−・アップダウンカウ
ンタ、７゜８・・・・・・比較回路、ＣＴ・・・・・・
カウント値、ＬＳ、 ＵＳ・・・・・・設定値。FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a timing chart thereof. 1.9...Flip-flop, 2,3.4.5
......Gate 6-----Up/down counter, 7゜8...Comparison circuit, CT...
Count value, LS, US... Setting value.
Claims (1)
タ手段と、このカウンタ手段の値を上下の予設定値と比
較しカウンタ手段の値が一方の設定値に達すると２値の
うち一方のレベル信号を出力し他め設定値に達すると２
値のうち他方のレベル信号を出力する手段と、入力信号
を２値化した値により上記カウンタ手段をカウントアツ
プ動作させるかカウントダウン動作させるかを決定する
手段とを具備する信号安定化回路。A counter means for counting up and down the clock, and comparing the value of this counter means with upper and lower preset values, and when the value of the counter means reaches one set value, outputs a level signal of one of the two values. 2 when the set value is reached
A signal stabilizing circuit comprising means for outputting a level signal of the other of the values, and means for determining whether to cause the counter means to perform a count-up operation or a count-down operation based on a value obtained by converting the input signal into a binary value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13827381U JPS5850738U (en) | 1981-09-19 | 1981-09-19 | signal stabilization circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13827381U JPS5850738U (en) | 1981-09-19 | 1981-09-19 | signal stabilization circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5850738U true JPS5850738U (en) | 1983-04-06 |
Family
ID=29931500
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13827381U Pending JPS5850738U (en) | 1981-09-19 | 1981-09-19 | signal stabilization circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850738U (en) |
-
1981
- 1981-09-19 JP JP13827381U patent/JPS5850738U/en active Pending
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