JPS6113398U - integrated circuit - Google Patents
integrated circuitInfo
- Publication number
- JPS6113398U JPS6113398U JP9360684U JP9360684U JPS6113398U JP S6113398 U JPS6113398 U JP S6113398U JP 9360684 U JP9360684 U JP 9360684U JP 9360684 U JP9360684 U JP 9360684U JP S6113398 U JPS6113398 U JP S6113398U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- integrated circuit
- latch
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案の一実施例によるブロック図、第2図は
本考案の他の実施例によるブロック図である。
第3図は従来の読み出し回路を示すブロック図である。
10・・・・・・記憶回路、20・・曲出力バッフナ、
30・・・・・・ラッチ回路、40・・・・・−NOR
ゲート、5o・・・・・・ラッチ回路。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of another embodiment of the present invention. FIG. 3 is a block diagram showing a conventional readout circuit. 10... Memory circuit, 20... Song output buffer,
30...Latch circuit, 40...-NOR
Gate, 5o...Latch circuit.
Claims (1)
の動作によって内容が変化する記憶回路を有し、該記憶
回路の記憶内容のうち少なくとも一部を前記論理回路の
動作に非同期な外部信号によって外部から読出すことが
できる集積回路に於で、前記記憶回路の内容が前記クロ
ツク信号に同期した信号で読込まれるラッチを介して外
部へ読出され、このラッチの信号読込みは前記外部信号
によって禁止されることを特徴とする集積回路。 2 前記ラッチの読み込みの禁止は前記外部信号を前記
クロツク信号に同期した信号でサンプリングした信号で
行なわれることを特徴とする実用新案登一請求の範囲第
1項記載の集積回路。[Claims for Utility Model Registration] 1. A memory circuit that incorporates a logic circuit operated by a clock signal and whose contents change depending on the operation of the internal circuit, and at least a part of the memory contents of the memory circuit are stored in the logic circuit. In an integrated circuit whose operation can be read externally by an external signal asynchronous to the operation, the contents of the memory circuit are read externally through a latch which is read by a signal synchronized with the clock signal, and the signal of this latch is An integrated circuit characterized in that reading is prohibited by the external signal. 2. The integrated circuit according to claim 1, wherein the prohibition of reading of the latch is performed using a signal obtained by sampling the external signal with a signal synchronized with the clock signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9360684U JPS6113398U (en) | 1984-06-22 | 1984-06-22 | integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9360684U JPS6113398U (en) | 1984-06-22 | 1984-06-22 | integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6113398U true JPS6113398U (en) | 1986-01-25 |
Family
ID=30651437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9360684U Pending JPS6113398U (en) | 1984-06-22 | 1984-06-22 | integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6113398U (en) |
-
1984
- 1984-06-22 JP JP9360684U patent/JPS6113398U/en active Pending
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