JPS59134948U - Working/standby switching logic circuit - Google Patents
Working/standby switching logic circuitInfo
- Publication number
- JPS59134948U JPS59134948U JP2666283U JP2666283U JPS59134948U JP S59134948 U JPS59134948 U JP S59134948U JP 2666283 U JP2666283 U JP 2666283U JP 2666283 U JP2666283 U JP 2666283U JP S59134948 U JPS59134948 U JP S59134948U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- working
- switching logic
- logic circuit
- standby switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の切替論理回路の回路図、第２図は本考案
の実施例の回路図、第、３図ａｘｈ、第４図ａ−ｈは第
２図の切替動作が行われないときおよび行われたときの
動作波形図である。図におい −で、１． １’
・・・・・・アラーム信号入力端子、２．２′・・・・
・・切替信号出力端子、１１〜１６・・・・・・ＮＡＮ
Ｄ回路、１７・・・・・・ＥＸＯＲ回路、１８・・・・
・・抵抗器、１９・・・・・・コンデンサ、である。Fig. 1 is a circuit diagram of a conventional switching logic circuit, Fig. 2 is a circuit diagram of an embodiment of the present invention, Figs. FIG. In the figure -, 1. 1'
...Alarm signal input terminal, 2.2'...
...Switching signal output terminal, 11-16...NAN
D circuit, 17...EXOR circuit, 18...
...Resistor, 19...Capacitor.
Claims (1)
らアラーム信号の一方のみが入力されたことを検出する
排他的論理和回路と、この排他的論理和回路の出力を積
分する積分回路と、この積分回路の出力が所定値以上に
あったとき前記一方のアラーム信号を出力するゲート回
路と、このゲ、−ト回路により駆動され前記現用系およ
び予備系へ切替信号を供給するフリップフロップ回路と
を含む現用予備切替論理回路。an exclusive OR circuit that inputs each alarm signal from the active system and the backup system and detects that only one of these alarm signals is input; an integrator circuit that integrates the output of this exclusive OR circuit; a gate circuit that outputs one of the alarm signals when the output of the integrating circuit exceeds a predetermined value; and a flip-flop circuit that is driven by the gate circuit and supplies a switching signal to the working system and the standby system. Contains working and standby switching logic circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2666283U JPS59134948U (en) | 1983-02-25 | 1983-02-25 | Working/standby switching logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2666283U JPS59134948U (en) | 1983-02-25 | 1983-02-25 | Working/standby switching logic circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134948U true JPS59134948U (en) | 1984-09-08 |
Family
ID=30157570
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2666283U Pending JPS59134948U (en) | 1983-02-25 | 1983-02-25 | Working/standby switching logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134948U (en) |
-
1983
- 1983-02-25 JP JP2666283U patent/JPS59134948U/en active Pending
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